Re: support for FPU-less VAX?

[Mouse <mouse%Rodents-Montreal.ORG@localhost>]

>> on page 96 gave me the impression that the 70 F, D, G FP
>> instructions are not implemented on the 78034:

>> "The chip fully executes 181 instructions and provides microcode
>> operand parsing for 21 instructions that are emulated with
>> macrocode.  The chip passes 70 F, D, G floating point instructions
>> to a companion floating point chip.  The remaining 32 instructions
>> are fully emulated in macrocode."

>> I thought if the CFPA is missing, maybe the CPU will raise
>> exceptions for FP instructions for emulation to take place.

That sounds like the wording in the KA630 manual; my impression was
that neither chip, alone, was a VAX CPU, just at most a major part of
one.  But the KA630 uses the 78032, not the 78034; I don't know how
similar they are.  (The KA630's companion FPU chip is the 78132.)

> Ah, well. If we start talking about specific floating point formats,
> then yes.  There are some formats that are not supported by some
> CPUs, and will trap.

But I don't think F-floating is one of them, is it?  As of 1986, the
base instruction group included basic F-, D-, and G-floating support,
with H-floating optional and a few instructions (ACBx, EMODx, and
POLYx) optional for all floating-point formats.  But, looking at the
pre-1986 data, F-floating is present in all the processors - and is the
only floating-point type that is.

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