On 24/08/15 06:11, Michael L. Hitch wrote:
On Mon, 24 Aug 2015, Felix Deichmann wrote:Nevertheless, can anyone think of a procedure to determine the real cache size programmatically and reliably? Would be fun to compare different machines, also VLC and KA660.I think it should be easy. The ENABLE_BANK bits in BEHR register description shows how to detect if a bank has been disabled, so it looks like it should just be a matter of counting how many banks are enabled.Now that I have my VLC systems set up, I can test that.
I'm almost certain that one of the DECnis CPU card variants used the SOC. The chip was specced at 8KB of cache, in 8 banks. DECnis could get by with less and so was allocated chips that had 6 (iirc) working banks (and also didn't need the FPU part to work). That saved money because it allowed Hudson to ship chips that would otherwise have been scrapped.
VLC couldn't have got by without the FPU (I presume). Whether the system was built to accept not-100% functional cache or not I don't know. I've found an earlier spec for the KA44, which also uses the SOC and implies 8KB cache of which at least 6KB is likely to be functional. I think this may have been an earlier rev of the KA48 spec - I don't recall anything shipping that was a KA44 (but it's been a while ...). Mostly it refers to the SOC chip spec for the nitty gritty. I've looked but I don't seem to have that in either paper form or electronic form. I'm mildly surprised that I don't have that around somewhere ... maybe DECnis used a different chip after all?
Antonio arcarlini%iee.org@localhost