should we add SH4 code to mmeye locore.S?

[Andrius V <vezhlys%gmail.com@localhost>]

Hi,

We have two similar files evbsh3/locore.S and mmeye/locore.S with the
major difference between one having SH4 specific code (invalidate and
enable instruction and operand caches according to comment) and other
(mmeye) not. However, in 2011 support was added to the newer SH4 based
mmEye devices (see MMEYE_WLF config). Thus, the question comes if
should add "#ifdef SH4" blocks to mmeye locore.S as well now, in case
this code was SH4 generic and suits for both machines
(https://github.com/NetBSD/src/blob/trunk/sys/arch/evbsh3/evbsh3/locore.S#L180
and https://github.com/NetBSD/src/blob/trunk/sys/arch/evbsh3/evbsh3/locore.S#L231)?

Additionally, shouldn't second #ifdef SH4 block be moved a bit higher,
since XltoP2/CCR seemed to be related to SH4 blocks only:
===================================================================
RCS file: /cvsroot/src/sys/arch/evbsh3/evbsh3/locore.S,v
retrieving revision 1.16
diff -u -p -r1.16 locore.S
--- sys/arch/evbsh3/evbsh3/locore.S    29 Sep 2023 06:09:20 -0000    1.16
+++ sys/arch/evbsh3/evbsh3/locore.S    30 Sep 2023 19:50:15 -0000
@@ -226,9 +226,9 @@ _ROM_START:    .long    IOM_ROM_BEGIN
 #endif
 XLinitSH3:    .long    _C_LABEL(initSH3)
 XLmain:        .long    _C_LABEL(main)
+#ifdef SH4    /* invalidate and enable instruction and operand caches */
 XLtoP2:        .long    0x20000000
 REG_SYMBOL(CCR)
-#ifdef SH4    /* invalidate and enable instruction and operand caches */
 XL_CCRVAL:    .long    SH4_CCR_ICI | SH4_CCR_ICE | SH4_CCR_OCI | SH4_CCR_OCE
 #endif /* SH4 */

Regards,
Andrius V