Re: X segfault

[T <bobs%thelibertytree.org@localhost>]

Installed debug sets and this is the traceback and pcictl information. 
This is for NetBSD 9.3_STABLE:

[Switching to LWP 1 of process 649]
fast_remainder32 (_s2=<optimized out>, _s1=<optimized out>, _m=<optimized 
out>, _div=<optimized out>, _v=<optimized out>) at /usr/obj/prep/netbsd-9/
destdir/usr/include/sys/bitops.h:294
294     /usr/obj/prep/netbsd-9/destdir/usr/include/sys/bitops.h: No such 
file or directory.
(gdb) cont
Continuing.

Program received signal SIGILL, Illegal instruction.
0xfd9a2940 in OPENSSL_ppc64_probe () from /usr/lib/libcrypto.so.14
(gdb) cont
Continuing.

Program received signal SIGILL, Illegal instruction.
0xfd9a2940 in OPENSSL_ppc64_probe () from /usr/lib/libcrypto.so.14
(gdb) cont
Continuing.

Program received signal SIGILL, Illegal instruction.
0xfd9a2960 in OPENSSL_altivec_probe () from /usr/lib/libcrypto.so.14
(gdb) cont
Continuing.

Program received signal SIGILL, Illegal instruction.
0xfd9a2960 in OPENSSL_altivec_probe () from /usr/lib/libcrypto.so.14
(gdb) cont
Continuing.

Program received signal SIGILL, Illegal instruction.
0xfd9a29a4 in OPENSSL_madd300_probe () from /usr/lib/libcrypto.so.14
(gdb) cont
Continuing.

Program received signal SIGILL, Illegal instruction.
0xfd9a29a4 in OPENSSL_madd300_probe () from /usr/lib/libcrypto.so.14
(gdb) cont
Continuing.

Program received signal SIGSEGV, Segmentation fault.
pci_io_read8 (handle=0x0, reg=reg@entry=972) at /usr/xsrc/external/mit/
libpciaccess/dist/src/common_io.c:184
184     /usr/xsrc/external/mit/libpciaccess/dist/src/common_io.c: No such 
file or directory.
(gdb) bt
#0  pci_io_read8 (handle=0x0, reg=reg@entry=972)
    at /usr/xsrc/external/mit/libpciaccess/dist/src/common_io.c:184
#1  0xfca11c60 in stdReadMiscOut (hwp=<optimized out>)
    at /usr/xsrc/external/mit/xorg-server/dist/hw/xfree86/vgahw/vgaHW.c:
262
#2  0xfca14e90 in vgaHWGetIOBase (hwp=hwp@entry=0xfcb5c700)
    at /usr/xsrc/external/mit/xorg-server/dist/hw/xfree86/vgahw/vgaHW.c:
1790
#3  0xfca876d8 in S3PreInit (pScrn=0xfdc3c800, flags=<optimized out>)
    at /usr/xsrc/external/mit/xf86-video-s3/dist/src/s3_driver.c:328
#4  0x0189c140 in InitOutput ()
#5  0x0182eab8 in dix_main ()
#6  0x0182e884 in ___start ()
#7  0x0182e65c in _start ()



# pcictl /dev/pci0 dump -b 000 -d 14 |more
PCI configuration registers:
  Common header:
    0x00: 0x88c15333 0x02000003 0x00010000 0x00000000

    Vendor Name: S3 (0x5333)
    Device Name: 86C864-1 ("Vision864") (0x88c1)
    Command register: 0x0003
      I/O space accesses: on
      Memory space accesses: on
      Bus mastering: off
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
      Interrupt disable: off
    Status register: 0x0200
      Immediate Readiness: off
      Interrupt status: inactive
      Capability List support: off
      66 MHz capable: off
      User Definable Features (UDF) support: off
      Fast back-to-back capable: off
      Data parity error detected: off
      DEVSEL timing: medium (0x1)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: prehistoric (0x00)
    Subclass Name: VGA (0x01)
    Interface: 0x00
    Revision ID: 0x00
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0x00
    Cache Line Size: 0bytes (0x00)

  Type 0 ("normal" device) header:
    0x10: 0x00000000 0x00000000 0x00000000 0x00000000
    0x20: 0x00000000 0x00000000 0x00000000 0x00000000
    0x30: 0x00850000 0x00000000 0x00000000 0x00000000

    Base address register at 0x10
      not implemented
    Base address register at 0x14
      not implemented
    Base address register at 0x18
      not implemented
    Base address register at 0x1c
      not implemented
    Base address register at 0x20
      not implemented
    Base address register at 0x24
      not implemented
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x0000
    Subsystem ID: 0x0000
    Expansion ROM Base Address Register: 0x00850000
      base: 0x00850000
      Expansion ROM Enable: off
      Validation Status: Validation not supported
      Validation Details: 0x0
    Reserved @ 0x34: 0x00000000
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x00
    Interrupt pin: 0x00 (none)
    Interrupt line: 0x00

  Device-dependent header:
    0x40: 0x00000000 0x00000000 0x00000000 0x00000000
    0x50: 0x00000000 0x00000000 0x00000000 0x00000000
    0x60: 0x00000000 0x00000000 0x00000000 0x00000000
    0x70: 0x00000000 0x00000000 0x00000000 0x00000000
    0x80: 0x00000000 0x00000000 0x00000000 0x00000000
    0x90: 0x00000000 0x00000000 0x00000000 0x00000000
    0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0x00000000 0x00000000 0x00000000