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Re: marvell relation support 20100413
Hi! Frank,
From: Frank Wille <frank%phoenix.owl.de@localhost>
Date: Fri, 07 May 2010 19:40:35 +0200
> KIYOHARA Takashi wrote:
> > Can you operate the some registers? (ex. GT_CPU_Mode,
> > GT_CPU_Master_Ctl, GT_CPU_Cfg)
>
> I printed those three registers during gt attachment and enabled DEBUG. Hope
> this helps:
>
> gt0 at mainbus0: MV6436x Discovery II
> CPU_Mode=00000043 CPU_Master_Ctl=00000b00 CPU_Cfg=000020ff
> gt0: scs[0]= 0-0xffffffff
> gt0: scs[1]= 0- 0xfffff
> gt0: scs[2]= 0- 0xfffff
> gt0: scs[3]= 0- 0xfffff
Your and my difference is CPU_Mode, CPU_Master_Ctl, and DRAM slots.
However, there is perhaps no problem.
CPU_Mode=00000050 CPU_Master_Ctl=00003b00
gt0: scs[0]= 0- 0xfffff
gt0: scs[1]= 0- 0xfffff
gt0: scs[2]= 0-0xffffffff
gt0: scs[3]= 0-0xffffffff
Moreover, gtpci overwrites some registers. Can you try with attached
patch?
My results:
gtpci0 at gt0 unit 0: Marvell PCI Interface
gtpci_init: line 237: GTPCI_BARE=0xfffffdf3
gtpci_init: line 242: GTPCI_AC=0x801f0030
gtpci_barinit: line 324: P2PC=0xff
gtpci_barinit: line 328: BARS=0x0
gtpci_barinit: line 328: BARS=0x0
gtpci_barinit: line 328: BARS=0xffff000
gtpci_barinit: line 328: BARS=0xffff000
gtpci_barinit: line 332: rv=0, base=0x0, size=0x0
gtpci_barinit: line 332: rv=0, base=0x0, size=0x0
gtpci_barinit: line 332: rv=0, base=0x10000000, size=0x10000000
gtpci_barinit: line 332: rv=0, base=0x0, size=0x10000000
gtpci_barinit: line 357: overwrite GTPCI_BARE=0xfffffff3
gtpci_protinit: line 468: prot 0, ACBL=0x9, ACBH=0x0, ACS=0x1ffff000
gtpci_protinit: line 468: prot 1, ACBL=0x0, ACBH=0x0, ACS=0x0
gtpci_protinit: line 468: prot 2, ACBL=0x0, ACBH=0x0, ACS=0x0
gtpci_protinit: line 468: prot 3, ACBL=0x0, ACBH=0x0, ACS=0x0
gtpci_protinit: line 468: prot 4, ACBL=0x0, ACBH=0x0, ACS=0x0
gtpci_protinit: line 468: prot 5, ACBL=0x0, ACBH=0x0, ACS=0x0
gtpci_init: line 250: GTPCI_ADC=0x8
gtpci_init: line 256: GTPCI_C=0x6e370
gtpci_pci_config: line 545: C=0x6e370
pci0 at gtpci0
gtpci1 at gt0 unit 1: Marvell PCI Interface
gtpci_init: line 237: GTPCI_BARE=0xfffff5f3
gtpci_init: line 242: GTPCI_AC=0x80000030
gtpci_barinit: line 324: P2PC=0xff
gtpci_barinit: line 328: BARS=0x0
gtpci_barinit: line 328: BARS=0x0
gtpci_barinit: line 328: BARS=0xffff000
gtpci_barinit: line 328: BARS=0xffff000
gtpci_barinit: line 332: rv=0, base=0x0, size=0x0
gtpci_barinit: line 332: rv=0, base=0x0, size=0x0
gtpci_barinit: line 332: rv=0, base=0x10000000, size=0x10000000
gtpci_barinit: line 332: rv=0, base=0x0, size=0x10000000
gtpci_barinit: line 357: overwrite GTPCI_BARE=0xfffffff3
gtpci_protinit: line 468: prot 0, ACBL=0x809, ACBH=0x0, ACS=0x1ffff000
gtpci_protinit: line 468: prot 1, ACBL=0x0, ACBH=0x0, ACS=0x0
gtpci_protinit: line 468: prot 2, ACBL=0x0, ACBH=0x0, ACS=0x0
gtpci_protinit: line 468: prot 3, ACBL=0x0, ACBH=0x0, ACS=0x0
gtpci_protinit: line 468: prot 4, ACBL=0x0, ACBH=0x0, ACS=0x0
gtpci_protinit: line 468: prot 5, ACBL=0x0, ACBH=0x0, ACS=0x0
gtpci_init: line 250: GTPCI_ADC=0x8
gtpci_init: line 256: GTPCI_C=0x6e140
gtpci_pci_config: line 545: C=0x6e140
pci1 at gtpci1
Thanks,
--
kiyohara
Index: gtpci.c
===================================================================
RCS file: /cvsroot/src/sys/dev/marvell/gtpci.c,v
retrieving revision 1.22
diff -u -r1.22 gtpci.c
--- gtpci.c 28 Apr 2010 13:51:56 -0000 1.22
+++ gtpci.c 8 May 2010 03:48:31 -0000
@@ -234,10 +234,12 @@
uint32_t reg;
/* First, all disable. Also WA CQ 4382 (bit15 must set 1)*/
+printf("%s: line %d: GTPCI_BARE=0x%x\n", __func__, __LINE__, GTPCI_READ(sc,
GTPCI_BARE));
GTPCI_WRITE(sc, GTPCI_BARE, GTPCI_BARE_ALLDISABLE | (1 << 15));
/* Enable Internal Arbiter */
reg = GTPCI_READ(sc, GTPCI_AC);
+printf("%s: line %d: GTPCI_AC=0x%x\n", __func__, __LINE__, GTPCI_READ(sc,
GTPCI_AC));
reg |= GTPCI_AC_EN;
GTPCI_WRITE(sc, GTPCI_AC, reg);
@@ -245,11 +247,13 @@
gtpci_protinit(sc);
reg = GTPCI_READ(sc, GTPCI_ADC);
+printf("%s: line %d: GTPCI_ADC=0x%x\n", __func__, __LINE__, GTPCI_READ(sc,
GTPCI_ADC));
reg |= GTPCI_ADC_REMAPWRDIS;
GTPCI_WRITE(sc, GTPCI_ADC, reg);
/* enable CPU-2-PCI ordering */
reg = GTPCI_READ(sc, GTPCI_C);
+printf("%s: line %d: GTPCI_C=0x%x\n", __func__, __LINE__, GTPCI_READ(sc,
GTPCI_C));
reg |= GTPCI_C_CPU2PCIORDERING;
GTPCI_WRITE(sc, GTPCI_C, reg);
}
@@ -317,11 +321,15 @@
p2pc = GTPCI_READ(sc, GTPCI_P2PC);
bus = GTPCI_P2PC_BUSNUMBER(p2pc);
dev = GTPCI_P2PC_DEVNUM(p2pc);
+printf("%s: line %d: P2PC=0x%x\n", __func__, __LINE__, p2pc);
bare = GTPCI_BARE_ALLDISABLE;
+for (map = 0; maps[map].tag != MARVELL_TAG_UNDEFINED; map++)
+printf("%s: line %d: BARS=0x%x\n", __func__, __LINE__,
bus_space_read_4(sc->sc_iot, sc->sc_ioh, maps[map].bars[sc->sc_unit]));
for (map = 0; maps[map].tag != MARVELL_TAG_UNDEFINED; map++) {
rv = marvell_winparams_by_tag(pdev, maps[map].tag, NULL, NULL,
&base, &size);
+printf("%s: line %d: rv=%d, base=0x%llx, size=0x%x\n", __func__, __LINE__, rv,
base, size);
if (rv != 0 || size == 0)
continue;
@@ -346,6 +354,7 @@
}
#endif
}
+printf("%s: line %d: overwrite GTPCI_BARE=0x%x\n", __func__, __LINE__, bare);
GTPCI_WRITE(sc, GTPCI_BARE, bare);
}
@@ -456,6 +465,10 @@
acsize += size;
}
+printf("%s: line %d: prot %d, ACBL=0x%x, ACBH=0x%x, ACS=0x%x\n", __func__,
__LINE__, prot,
+bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_ACBL(sc->sc_unit, prot)),
+bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_ACBH(sc->sc_unit, prot)),
+bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_ACS(sc->sc_unit, prot)));
if (acsize != 0) {
GTPCI_WRITE_AC(sc, GTPCI_ACBL, prot,
((acbase & 0xffffffff) >> acbl_base_rshift) |
@@ -529,6 +542,7 @@
} else
pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
command = GTPCI_READ(sc, GTPCI_C);
+printf("%s: line %d: C=0x%x\n", __func__, __LINE__, command);
if (command & GTPCI_C_MRDMUL)
pba.pba_flags |= PCI_FLAGS_MRM_OKAY;
if (command & GTPCI_C_MRDLINE)
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