SMP in ppcoea-renovation

[Michael Lorenz <macallan%netbsd.org@localhost>]

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Hello,

now that I have a dual G4 box I gave ppcoea-renovation a shot. Here's  
what I found:
- - uniprocessor kernels seem to work just fine, as expected
- - SMP kernels don't compile but that's trivial to fix, the secondary  
CPU startup code tries to write to some OpenPIC register to make sure  
only the 1st CPU gets interrupts.
- - with those things fixed the kernel stops in cpu_spinup() when  
trying to reset the 2nd CPU via out8(gpio, 4)

The code looks ok to me, gpio is the same as in a 4.0 kernel which  
works. So I suspected missing or wrong BAT mappings for the gpio's  
address but changing oeaofw_ppcinit() back to use the same code as  
macppc in 4.0 didn't help.

So, what needs to be done is:
- - find out why out8(gpio, 4) hangs the machine
- - add an abstract interface for IPIs , hide information which vector  
to use etc. inside the PIC drivers, find a sane way to register IPI  
handlers.
- - deal with special cases where only CPU0 can handle interrupts like  
with legacy Apple PICs. Find out if that's a hardware limitation or  
just laziness. Unfortunately I don't have an Old World SMP box.
- - do we need to add locking to interrupt handling code? At least with  
Old World PICs we probably have to if we want both CPUs to take  
interrupt. OpenPIC seems to do something like that in hardware?

have fun
Michael
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