Subject: Re: evbppc reserved-tlb cleanup
To: None <freza@dspfpga.com, port-powerpc@netbsd.org>
From: FUKAUMI Naoki <naoki@fukaumi.org>
List: port-powerpc
Date: 10/06/2006 15:45:57
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Hi Jachym Holecek,
http://mail-index.netbsd.org/port-powerpc/2006/09/24/0000.html
http://mail-index.netbsd.org/port-powerpc/2006/09/24/0006.html
These two patch is not enough for OpenBlockS266.
I've added following fixes,
- change arch/powerpc/ibm4xx/openbios/locore.S too for OBS266
- use OBS405_CONADDR instead of 0xef000000
- don't call consinit() in obs2{00,66}_machdep.c because consinit() is
already called in ibm4xx_init() (but I'm not sure which place is
good)
- do bus_space_map() to get bus space handle in emacs_attach() (!!!)
then OpenBlockS266 boots correctly.
Attached patch is your 2 patch + my fixes. s/0x74000000/BASE_ISA/ is not
included. (sorry)
--
FUKAUMI Naoki
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diff -ur src.orig/sys/arch/evbppc/explora/machdep.c src/sys/arch/evbppc/explora/machdep.c
--- src.orig/sys/arch/evbppc/explora/machdep.c 2006-09-19 07:05:47.000000000 +0900
+++ src/sys/arch/evbppc/explora/machdep.c 2006-10-06 13:49:44.000000000 +0900
@@ -134,26 +134,6 @@
#endif /* DDB */
};
-static void
-set_tlb(int idx, u_int addr, u_int flags)
-{
- u_int lo, hi;
-
- addr &= ~(TLB_PG_SIZE-1);
-
- lo = addr | TLB_EX | TLB_WR | flags;
-#ifdef PPC_4XX_NOCACHE
- lo |= TLB_I;
-#endif
- hi = addr | TLB_VALID | TLB_PG_16M;
-
- __asm volatile(
- " tlbwe %1,%0,1 \n"
- " tlbwe %2,%0,0 \n"
- " sync \n"
- : : "r" (idx), "r" (lo), "r" (hi) );
-}
-
/*
* Install a trap vector. We cannot use memcpy because the
* destination may be zero.
@@ -174,11 +154,9 @@
bootstrap(u_int startkernel, u_int endkernel)
{
u_int i, j, t, br[4];
- u_int ntlb, maddr, msize, size;
+ u_int maddr, msize, size;
struct cpu_info * const ci = &cpu_info[0];
- consinit();
-
br[0] = mfdcr(DCR_BR4);
br[1] = mfdcr(DCR_BR5);
br[2] = mfdcr(DCR_BR6);
@@ -198,14 +176,6 @@
size = maddr+msize;
}
-#ifdef COM_IS_CONSOLE
- ntlb = TLB_NRESERVED-1;
-#else
- ntlb = TLB_NRESERVED-2;
-#endif
- if (size > ntlb*TLB_PG_SIZE)
- size = ntlb*TLB_PG_SIZE;
-
phys_mem[0].start = 0;
phys_mem[0].size = size & ~PGOFSET;
avail_mem[0].start = startkernel;
@@ -214,7 +184,7 @@
__asm volatile(
" mtpid %0 \n"
" sync \n"
- : : "r" (1) );
+ : : "r" (KERNEL_PID) );
/*
* Setup initial tlbs.
@@ -224,15 +194,18 @@
t = 0;
for (maddr = 0; maddr < phys_mem[0].size; maddr += TLB_PG_SIZE)
- set_tlb(t++, maddr, 0);
+ ppc4xx_tlb_reserve(maddr, maddr, TLB_PG_SIZE, TLB_EX);
-#ifdef COM_IS_CONSOLE
- set_tlb(t++, BASE_COM, TLB_I | TLB_G);
-#else
- set_tlb(t++, BASE_FB, TLB_I | TLB_G);
- set_tlb(t++, BASE_FB2, TLB_I | TLB_G);
+ /* Map PCKBC, PCKBC2, COM, LPT. */
+ ppc4xx_tlb_reserve(0x74000000, 0x74000000, TLB_PG_SIZE, TLB_I | TLB_G);
+
+#ifndef COM_IS_CONSOLE
+ ppc4xx_tlb_reserve(BASE_FB, BASE_FB, TLB_PG_SIZE, TLB_I | TLB_G);
+ ppc4xx_tlb_reserve(BASE_FB2, BASE_FB2, TLB_PG_SIZE, TLB_I | TLB_G);
#endif
+ consinit();
+
/* Disable all external interrupts */
mtdcr(DCR_EXIER, 0);
diff -ur src.orig/sys/arch/evbppc/obs405/obs200_locore.S src/sys/arch/evbppc/obs405/obs200_locore.S
--- src.orig/sys/arch/evbppc/obs405/obs200_locore.S 2006-07-01 02:54:50.000000000 +0900
+++ src/sys/arch/evbppc/obs405/obs200_locore.S 2006-10-06 13:48:19.000000000 +0900
@@ -190,59 +190,11 @@
stw %r8,0(%r7)
#endif
- /*
- * Set up TLB entry to cover kernel addresses.
- *
- * XXX: Skip TLB 0 for now, due to unresolved TLB 0 replacement
- * and hard hangs
- */
- li %r0,1
+ /* Set kernel MMU context. */
+ li %r0,KERNEL_PID
mtpid %r0
sync
- li %r0,0
-#ifdef PPC_4XX_NOCACHE
- li %r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
-#else
- li %r4,TLB_EX|TLB_WR /* |TLB_W */
-#endif
- li %r3,TLB_VALID|TLB_PG_16M
- tlbwe %r4,%r0,1 /* Load the data(Low) portion of the entry */
- tlbwe %r3,%r0,0 /* Load the tag(High) portion of the entry */
-
-#if 1
- /* Damn. Have to be able to access all real memory.... Hardcode for 32M for now. */
- li %r0,1
- lis %r4,0x01000000@h
- ori %r3,%r4,0
-#ifdef PPC_4XX_NOCACHE
- addi %r4,%r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
-#else
- addi %r4,%r4,TLB_EX|TLB_WR /* |TLB_W */
-#endif
- addi %r3,%r3,TLB_VALID|TLB_PG_16M
- tlbwe %r4,%r0,1 /* Load the data(Low) portion of the entry */
- tlbwe %r3,%r0,0 /* Load the tag(High) portion of the entry */
-#endif
-
- /* set up a TLB mapping to cover uart0 */
- lis %r3,0xef000000@h /* Load the virtual address */
- ori %r4,%r3,0 /* Load the physical address */
-
- clrrwi %r4,%r4,10 /* Mask off the real page number */
- /* write, execute, cache inhibit, guarded */
- ori %r4,%r4,(TLB_WR|TLB_EX|TLB_I|TLB_G)
-
- clrrwi %r3,%r3,10 /* Mask off the effective page number */
- ori %r3,%r3,(TLB_VALID|TLB_PG_16M)
-
- li %r0,2
-
- tlbwe %r4,%r0,1 /* Load the data portion of the entry */
- tlbwe %r3,%r0,0 /* Load the tag portion of the entry */
-
- /* END of TLB setup */
-
INIT_CPUINFO(8,1,9,0)
mr %r4,%r8
diff -ur src.orig/sys/arch/evbppc/obs405/obs200_machdep.c src/sys/arch/evbppc/obs405/obs200_machdep.c
--- src.orig/sys/arch/evbppc/obs405/obs200_machdep.c 2006-03-30 02:50:33.000000000 +0900
+++ src/sys/arch/evbppc/obs405/obs200_machdep.c 2006-10-06 15:06:51.000000000 +0900
@@ -97,6 +97,9 @@
#include "ksyms.h"
+
+#define TLB_PG_SIZE (16*1024*1024)
+
/*
* Global variables used here and there
*/
@@ -117,6 +120,7 @@
{
u_int32_t pllmode;
u_int32_t psr;
+ vaddr_t va;
u_int memsize;
/* Disable all external interrupts */
@@ -128,16 +132,18 @@
bios_board_init(info_block, startkernel);
memsize = bios_board_memsize_get();
+ /* Linear map whole physmem. */
+ for (va = 0; va < memsize; va += TLB_PG_SIZE)
+ ppc4xx_tlb_reserve(va, va, TLB_PG_SIZE, TLB_EX);
+
+ /* Map console right after RAM. */
+ ppc4xx_tlb_reserve(OBS405_CONADDR, va, TLB_PG_SIZE, TLB_I | TLB_G);
+
/* Initialize IBM405GPr CPU */
ibm40x_memsize_init(memsize, startkernel);
ibm4xx_init((void (*)(void))ext_intr);
/*
- * Initialize console.
- */
- consinit();
-
- /*
* Set the page size.
*/
uvm_setpagesize();
diff -ur src.orig/sys/arch/evbppc/obs405/obs266_machdep.c src/sys/arch/evbppc/obs405/obs266_machdep.c
--- src.orig/sys/arch/evbppc/obs405/obs266_machdep.c 2006-03-30 02:50:33.000000000 +0900
+++ src/sys/arch/evbppc/obs405/obs266_machdep.c 2006-10-06 14:07:37.000000000 +0900
@@ -97,6 +97,9 @@
#include "ksyms.h"
+
+#define TLB_PG_SIZE (16*1024*1024)
+
/*
* Global variables used here and there
*/
@@ -115,6 +118,7 @@
void
initppc(u_int startkernel, u_int endkernel, char *args, void *info_block)
{
+ vaddr_t va;
u_int memsize;
/* Disable all external interrupts */
@@ -124,16 +128,18 @@
openbios_board_init(info_block, startkernel);
memsize = openbios_board_memsize_get();
+ /* Linear map whole physmem */
+ for (va = 0; va < memsize; va += TLB_PG_SIZE)
+ ppc4xx_tlb_reserve(va, va, TLB_PG_SIZE, TLB_EX);
+
+ /* Map console just after RAM */
+ ppc4xx_tlb_reserve(OBS405_CONADDR, va, TLB_PG_SIZE, TLB_I | TLB_G);
+
/* Initialize IBM405GPr CPU */
ibm40x_memsize_init(memsize, startkernel);
ibm4xx_init((void (*)(void))ext_intr);
/*
- * Initialize console.
- */
- consinit();
-
- /*
* Set the page size.
*/
uvm_setpagesize();
diff -ur src.orig/sys/arch/evbppc/walnut/machdep.c src/sys/arch/evbppc/walnut/machdep.c
--- src.orig/sys/arch/evbppc/walnut/machdep.c 2006-07-13 16:36:04.000000000 +0900
+++ src/sys/arch/evbppc/walnut/machdep.c 2006-10-06 13:48:19.000000000 +0900
@@ -115,6 +115,9 @@
#include <ddb/db_extern.h>
#endif
+
+#define TLB_PG_SIZE (16*1024*1024)
+
/*
* Global variables used here and there
*/
@@ -171,6 +174,7 @@
#ifdef IPKDB
extern int ipkdblow, ipkdbsize;
#endif
+ vaddr_t va;
int exc, dbcr0;
struct cpu_info * const ci = curcpu();
@@ -191,6 +195,13 @@
availmemr[0].start = startkernel;
availmemr[0].size = board_data.mem_size - availmemr[0].start;
+ /* Linear map whole physmem */
+ for (va = 0; va < board_data.mem_size; va += TLB_PG_SIZE)
+ ppc4xx_tlb_reserve(va, va, TLB_PG_SIZE, TLB_EX);
+
+ /* Map console just after RAM */
+ ppc4xx_tlb_reserve(0xef000000, va, TLB_PG_SIZE, TLB_I | TLB_G);
+
/*
* Initialize lwp0 and current pcb and pmap pointers.
*/
diff -ur src.orig/sys/arch/evbppc/walnut/walnut_start.S src/sys/arch/evbppc/walnut/walnut_start.S
--- src.orig/sys/arch/evbppc/walnut/walnut_start.S 2006-07-01 02:54:51.000000000 +0900
+++ src/sys/arch/evbppc/walnut/walnut_start.S 2006-10-06 13:48:19.000000000 +0900
@@ -192,59 +192,11 @@
stw %r8,0(%r7)
#endif
- /*
- * Set up TLB entry to cover kernel addresses.
- *
- * XXX: Skip TLB 0 for now, due to unresolved TLB 0 replacement
- * and hard hangs
- */
- li %r0,1
+ /* Set kernel MMU context. */
+ li %r0,KERNEL_PID
mtpid %r0
sync
- li %r0,0
-#ifdef PPC_4XX_NOCACHE
- li %r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
-#else
- li %r4,TLB_EX|TLB_WR /* |TLB_W */
-#endif
- li %r3,TLB_VALID|TLB_PG_16M
- tlbwe %r4,%r0,1 /* Load the data(Low) portion of the entry */
- tlbwe %r3,%r0,0 /* Load the tag(High) portion of the entry */
-
-#if 1
- /* Damn. Have to be able to access all real memory.... Hardcode for 32M for now. */
- li %r0,1
- lis %r4,0x01000000@h
- ori %r3,%r4,0
-#ifdef PPC_4XX_NOCACHE
- addi %r4,%r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
-#else
- addi %r4,%r4,TLB_EX|TLB_WR /* |TLB_W */
-#endif
- addi %r3,%r3,TLB_VALID|TLB_PG_16M
- tlbwe %r4,%r0,1 /* Load the data(Low) portion of the entry */
- tlbwe %r3,%r0,0 /* Load the tag(High) portion of the entry */
-#endif
-
- /* set up a TLB mapping to cover uart0 */
- lis %r3,0xef000000@h /* Load the virtual address */
- ori %r4,%r3,0 /* Load the physical address */
-
- clrrwi %r4,%r4,10 /* Mask off the real page number */
- /* write, execute, cache inhibit, guarded */
- ori %r4,%r4,(TLB_WR|TLB_EX|TLB_I|TLB_G)
-
- clrrwi %r3,%r3,10 /* Mask off the effective page number */
- ori %r3,%r3,(TLB_VALID|TLB_PG_16M)
-
- li %r0,2
-
- tlbwe %r4,%r0,1 /* Load the data portion of the entry */
- tlbwe %r3,%r0,0 /* Load the tag portion of the entry */
-
- /* END of TLB setup */
-
INIT_CPUINFO(8,1,9,0)
mr %r4,%r8
diff -ur src.orig/sys/arch/powerpc/ibm4xx/dev/emacreg.h src/sys/arch/powerpc/ibm4xx/dev/emacreg.h
--- src.orig/sys/arch/powerpc/ibm4xx/dev/emacreg.h 2002-08-13 13:57:48.000000000 +0900
+++ src/sys/arch/powerpc/ibm4xx/dev/emacreg.h 2006-10-06 15:01:42.000000000 +0900
@@ -38,6 +38,9 @@
#ifndef _IBM4XX_EMACREG_H_
#define _IBM4XX_EMACREG_H_
+/* Number of Ethernet MAC Registers */
+#define EMAC_NREG 0x70
+
/* Ethernet MAC Registers */
#define EMAC_MR0 0x00 /* Mode Register 0 */
#define MR0_RXI 0x80000000 /* Receive MAC Idle */
diff -ur src.orig/sys/arch/powerpc/ibm4xx/dev/if_emac.c src/sys/arch/powerpc/ibm4xx/dev/if_emac.c
--- src.orig/sys/arch/powerpc/ibm4xx/dev/if_emac.c 2006-05-06 03:04:42.000000000 +0900
+++ src/sys/arch/powerpc/ibm4xx/dev/if_emac.c 2006-10-06 15:01:52.000000000 +0900
@@ -307,8 +307,8 @@
const uint8_t *enaddr;
prop_data_t ea;
+ bus_space_map(oaa->opb_bt, oaa->opb_addr, EMAC_NREG, 0, &sc->sc_sh);
sc->sc_st = oaa->opb_bt;
- sc->sc_sh = oaa->opb_addr;
sc->sc_dmat = oaa->opb_dmat;
printf(": 405GP EMAC\n");
diff -ur src.orig/sys/arch/powerpc/ibm4xx/openbios/locore.S src/sys/arch/powerpc/ibm4xx/openbios/locore.S
--- src.orig/sys/arch/powerpc/ibm4xx/openbios/locore.S 2005-12-11 21:18:43.000000000 +0900
+++ src/sys/arch/powerpc/ibm4xx/openbios/locore.S 2006-10-06 13:55:19.000000000 +0900
@@ -210,59 +210,11 @@
stw %r8,0(%r7)
#endif
- /*
- * Set up TLB entry to cover kernel addresses.
- *
- * XXX: Skip TLB 0 for now, due to unresolved TLB 0 replacement
- * and hard hangs
- */
- li %r0,1
+ /* Set kernel MMU context. */
+ li %r0,KERNEL_PID
mtpid %r0
sync
- li %r0,0
-#ifdef PPC_4XX_NOCACHE
- li %r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
-#else
- li %r4,TLB_EX|TLB_WR /* |TLB_W */
-#endif
- li %r3,TLB_VALID|TLB_PG_16M
- tlbwe %r4,%r0,1 /* Load the data(Low) portion of the entry */
- tlbwe %r3,%r0,0 /* Load the tag(High) portion of the entry */
-
-#if 1
- /* Damn. Have to be able to access all real memory.... Hardcode for 32M for now. */
- li %r0,1
- lis %r4,0x01000000@h
- ori %r3,%r4,0
-#ifdef PPC_4XX_NOCACHE
- addi %r4,%r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
-#else
- addi %r4,%r4,TLB_EX|TLB_WR /* |TLB_W */
-#endif
- addi %r3,%r3,TLB_VALID|TLB_PG_16M
- tlbwe %r4,%r0,1 /* Load the data(Low) portion of the entry */
- tlbwe %r3,%r0,0 /* Load the tag(High) portion of the entry */
-#endif
-
- /* set up a TLB mapping to cover uart0 */
- lis %r3,0xef000000@h /* Load the virtual address */
- ori %r4,%r3,0 /* Load the physical address */
-
- clrrwi %r4,%r4,10 /* Mask off the real page number */
- /* write, execute, cache inhibit, guarded */
- ori %r4,%r4,(TLB_WR|TLB_EX|TLB_I|TLB_G)
-
- clrrwi %r3,%r3,10 /* Mask off the effective page number */
- ori %r3,%r3,(TLB_VALID|TLB_PG_16M)
-
- li %r0,2
-
- tlbwe %r4,%r0,1 /* Load the data portion of the entry */
- tlbwe %r3,%r0,0 /* Load the tag portion of the entry */
-
- /* END of TLB setup */
-
INIT_CPUINFO(8,1,9,0)
mr %r4,%r8
diff -ur src.orig/sys/arch/powerpc/ibm4xx/pmap.c src/sys/arch/powerpc/ibm4xx/pmap.c
--- src.orig/sys/arch/powerpc/ibm4xx/pmap.c 2006-09-01 07:13:51.000000000 +0900
+++ src/sys/arch/powerpc/ibm4xx/pmap.c 2006-10-06 13:48:19.000000000 +0900
@@ -267,10 +267,6 @@
int cnt, i;
u_int s, e, sz;
- /* XXXfreza: compat, we used to statically reserve 4 entries. */
- if (tlb_nreserved == 0)
- tlb_nreserved = TLB_NRESERVED;
-
tlbnext = tlb_nreserved;
/*
@@ -1454,7 +1450,7 @@
va &= ~(rsize - 1); /* EPN */
lo = pa | TLB_WR | flags;
- hi = va | TLB_VALID | szmask | KERNEL_PID;
+ hi = va | TLB_VALID | szmask;
#ifdef PPC_4XX_NOCACHE
lo |= TLB_I;
diff -ur src.orig/sys/arch/powerpc/include/ibm4xx/tlb.h src/sys/arch/powerpc/include/ibm4xx/tlb.h
--- src.orig/sys/arch/powerpc/include/ibm4xx/tlb.h 2006-09-01 07:13:51.000000000 +0900
+++ src/sys/arch/powerpc/include/ibm4xx/tlb.h 2006-10-06 13:48:19.000000000 +0900
@@ -109,6 +109,4 @@
#define TLB_PID_INVALID 0xFFFF
-#define TLB_NRESERVED 4 /* XXXfreza: kill. */
-
#endif /* _IBM4XX_TLB_H_ */
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