# Jachym Holecek 2006-09-24:
> # Izumi Tsutsui 2006-09-24:
> > freza@dspfpga.com wrote:
> > 
> > > Hmm, can you try moving consinit() after TLB setup? It doesn't matter
> > > whether you try with or without my patch. After recent mapiodev() changes,
> > > bus_space_map() must be called after reserved TLB entries were filled
> > > (back then, I overlooked Explora451 calls consinit() earlier than that,
> > > sorry for breakage).
> > 
> > I moved consinit() right after set_tlb()s in explora/machdep.c:bootstrap(),
> > now kernel got the following panic:
> > 
> > panic: mapiodev: no TLB entry reserved for 740000c0+2
> > Stopped at	0x2698fc:	lxz	r0, r1, 0x14
> > db> 
> > 
> > It looks pckbc also needs to be mapped.
> 
> Hmm, interesting it worked before (pckbc was never reserve-mapped ;-).
> I guess we can uncondionally map 0x7400'0000 -- 0x7500'0000 like below
> (patch against -current, see the very end).

... erm, this time with consinit() moved down as appropriate.

	-- Jachym

Index: explora/machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbppc/explora/machdep.c,v
retrieving revision 1.13
diff -d -p -u -r1.13 machdep.c
--- explora/machdep.c	18 Sep 2006 22:05:47 -0000	1.13
+++ explora/machdep.c	24 Sep 2006 13:44:23 -0000
@@ -134,26 +134,6 @@ static struct {
 #endif /* DDB */
 };
 
-static void
-set_tlb(int idx, u_int addr, u_int flags)
-{
-	u_int lo, hi;
-
-	addr &= ~(TLB_PG_SIZE-1);
-
-	lo = addr | TLB_EX | TLB_WR | flags;
-#ifdef PPC_4XX_NOCACHE
-	lo |= TLB_I;
-#endif
-	hi = addr | TLB_VALID | TLB_PG_16M;
-
-	__asm volatile(
-	    "	tlbwe %1,%0,1	\n"
-	    "	tlbwe %2,%0,0	\n"
-	    "	sync		\n"
-	    : : "r" (idx), "r" (lo), "r" (hi) );
-}
-
 /*
  * Install a trap vector. We cannot use memcpy because the
  * destination may be zero.
@@ -174,11 +154,9 @@ void
 bootstrap(u_int startkernel, u_int endkernel)
 {
 	u_int i, j, t, br[4];
-	u_int ntlb, maddr, msize, size;
+	u_int maddr, msize, size;
 	struct cpu_info * const ci = &cpu_info[0];
 
-	consinit();
-
 	br[0] = mfdcr(DCR_BR4);
 	br[1] = mfdcr(DCR_BR5);
 	br[2] = mfdcr(DCR_BR6);
@@ -198,14 +176,6 @@ bootstrap(u_int startkernel, u_int endke
 			size = maddr+msize;
 	}
 
-#ifdef COM_IS_CONSOLE
-	ntlb = TLB_NRESERVED-1;
-#else
-	ntlb = TLB_NRESERVED-2;
-#endif
-	if (size > ntlb*TLB_PG_SIZE)
-		size = ntlb*TLB_PG_SIZE;
-
 	phys_mem[0].start = 0;
 	phys_mem[0].size = size & ~PGOFSET;
 	avail_mem[0].start = startkernel;
@@ -214,7 +184,7 @@ bootstrap(u_int startkernel, u_int endke
 	__asm volatile(
 	    "	mtpid %0	\n"
 	    "	sync		\n"
-	    : : "r" (1) );
+	    : : "r" (KERNEL_PID) );
 
 	/*
 	 * Setup initial tlbs.
@@ -224,15 +194,18 @@ bootstrap(u_int startkernel, u_int endke
 
 	t = 0;
 	for (maddr = 0; maddr < phys_mem[0].size; maddr += TLB_PG_SIZE)
-		set_tlb(t++, maddr, 0);
+		ppc4xx_tlb_reserve(maddr, maddr, TLB_PG_SIZE, TLB_EX);
 
-#ifdef COM_IS_CONSOLE
-	set_tlb(t++, BASE_COM, TLB_I | TLB_G);
-#else
-	set_tlb(t++, BASE_FB, TLB_I | TLB_G);
-	set_tlb(t++, BASE_FB2, TLB_I | TLB_G);
+	/* Map PCKBC, PCKBC2, COM, LPT. */
+	ppc4xx_tlb_reserve(0x74000000, 0x74000000, TLB_PG_SIZE, TLB_I | TLB_G);
+
+#ifndef COM_IS_CONSOLE
+	ppc4xx_tlb_reserve(BASE_FB,  BASE_FB,  TLB_PG_SIZE, TLB_I | TLB_G);
+	ppc4xx_tlb_reserve(BASE_FB2, BASE_FB2, TLB_PG_SIZE, TLB_I | TLB_G);
 #endif
 
+	consinit();
+
 	/* Disable all external interrupts */
 	mtdcr(DCR_EXIER, 0);