7450 / 7455 L3 cache code

[John Klos <john%ziaspace.com@localhost>]

Hi,

I'm committing code to allow the manual configuration of L3 cache on 7450
/ 7455 based accelerators such as the Sonnet Crescendo PCI.

If you're tracking current, please give this a try. It might also be
worthwhile if someone could test a manual configuration on a new 745x
based G4 from Apple, just to make sure it generally works.

In order to test, use values from sys/arch/powerpc/include/spr.h in your
kernel config like this example:

options         L2CR_CONFIG="(L2CR_L2E)"
options         L3CR_CONFIG="(L3CLK_35|L3CKSP_4|L3PSP_0|L3RT_PB2_SRAM)"

This example gives me this on a 700 MHz 7455 with 256k of L2 cache and 1
meg of 200 MHz (700 MHz / 3.5) L3 cache:

cpu0 at mainbus0: 7450 (Revision 2.1), ID 0 (primary)
cpu0: HID0 8450c0a4<EMCP,TBEN,NAP,DPM,ICE,DCE,SGE,BTIC,BHT>
cpu0: 700.00 MHz
cpu0: 256KB L2 cache, 1MB L3 backside cache at 3.5:1 ratio

The files changed are sys/arch/powerpc/include/spr.h,
sys/arch/powerpc/conf/files.powerpc, and sys/arch/powerpc/oea/cpu_subr.c.

Thanks to Monroe Williams for the code. Yay for the fast-as-hell, under
$300 USD accelerator!

John Klos