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Re: bzero.S and assym.h (Re: CVS commit: syssrc/sys/lib/libkern/arch/powerpc)

To: Greg Lehey <grog%lemis.com@localhost>
Subject: Re: bzero.S and assym.h (Re: CVS commit: syssrc/sys/lib/libkern/arch/powerpc)
From: David Edelsohn <dje%watson.ibm.com@localhost>
Date: Mon, 03 Dec 2001 20:44:30 -0500

>>>>> Greg Lehey writes:

Greg> In general the 60x range has 32 bytes cache lines, embedded processors
Greg> (40x and 80x) have 16 bytes, and the 64 bit processors have 128 byte
Greg> cache lines.  There are exceptions, like the 405, which is a 64 bit
Greg> embedded processor and has 32 byte cache lines.

        The PPC405 is a 32-bit embedded processor.

David

Follow-Ups:
- Re: bzero.S and assym.h (Re: CVS commit: syssrc/sys/lib/libkern/arch/powerpc)
  - From: Greg Lehey

References:
- Re: bzero.S and assym.h (Re: CVS commit: syssrc/sys/lib/libkern/arch/powerpc)
  - From: Greg Lehey

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