Re: data and instruction caches

[p99dreyf%criens.u-psud.fr@localhost (Emmanuel Dreyfus)]

> >I have a question about data and instruction cache. I remember that except
> >for the PowerPC 601, they are distinct on the PowerPC architecture.
> >
> >How does it works with signal trampolines? The trampoline is treated as data
> >when it is copied on the stack , ands hence it fits in the data cache, but
> >when we branch to it, processor will look into the instruction cache, not the
> >data cache. Hence, if the data cache was not flushed, the processor may
> >brnach to a location on the stack where there is nothing yet.
> >
> >I assume there must be some cache handling somewhere, but where is it in the
> >code?
> 
> look for the syncicache code.  Basically, you do a isync (possibly
> preceded by a sync).

Ok I checked it, but it seems we don't use it directly.
We copy a signal trampoline using copyout(), which is defined in
sys/arch/powerpc/powerpc/trap.c

copyout() calls setusr(), defined in the same file. callusr() uses the
assembly instruction isync, then copyout() uses bcopy to actually
transfer the data.

Questions: is isync to flush instruction cache and sync to flush
processor cache?

Anyway, we flush a cache (instruction or data, I don't know), then we
copy. Where do we flush the data cache to ensure that when we branch, we
does not jump to a location where code has not been flushed yet from the
data cache?

There must be some sync/isync after exitting sendsig(), but I don't
really understand how it works when we get out of sendsig and before we
enter the signal trampoline on the stack. If someone can explain me...

-- 
Emmanuel Dreyfus
UNIX *is* user friendly. It is just a bit selective about his friends
p99dreyf%criens.u-psud.fr@localhost