data and instruction caches

[Emmanuel Dreyfus <p99dreyf%criens.u-psud.fr@localhost>]

Hello

I have a question about data and instruction cache. I remember that except
for the PowerPC 601, they are distinct on the PowerPC architecture.

How does it works with signal trampolines? The trampoline is treated as data
when it is copied on the stack , ands hence it fits in the data cache, but
when we branch to it, processor will look into the instruction cache, not the 
data cache. Hence, if the data cache was not flushed, the processor may
brnach to a location on the stack where there is nothing yet.

I assume there must be some cache handling somewhere, but where is it in the 
code?

-- 
Emmanuel Dreyfus
Pas de processeur Intel, pas de logiciel Microsoft:
Des programmes sains dans un ordinateur sain.
p99dreyf%criens.u-psud.fr@localhost