RE: Multi-Processor support

[Bill Rees <bill_rees%firepower.com@localhost>]

One of the words defined for mp OF implementations is cpu-execute that 
allows you to "wake up" the other cpu once the firmware has brought the
system up.  The first  thing the os load mechanism needs to do is bring up
the os to some level of sanity before adding the second, third, other cpus
into the group.  Generally, you will either need to talk to the cpu via the
open firmware client interface executing the method "cpu-execute" to point
the processor to the thread of initialization  the os provides.

One of the things we did on NT was to define an interface program that
mapped NT's load standard to Open Firmware.  This allows the firmware to
have minimal knowledge of NT and NT to have almost no knowledge of OF.

Typically, the master cpu is physical zero but not always guarenteed.

Bill Rees
FirePower Team,
Motorola Computer Group.

>----------
>From:  Jason Thorpe[SMTP:thorpej%nas.nasa.gov@localhost]
>Sent:  Wednesday, October 23, 1996 12:01 AM
>To:    Markus Illenseer
>Cc:    rhialto%polder.ubc.kun.nl@localhost; port-powerpc%NetBSD.ORG@localhost
>Subject:       Re: Multi-Processor support 
>
>On Wed, 23 Oct 1996 08:11:05 +0200 (MET DST) 
> Markus Illenseer <markus%server.peacock.de@localhost> wrote:
>
> >  Currently I do not know how to deal with two processors, I believe that
> > you need to enable SMP (that is symetric multiprocessing) anyway, so
> > by default only one CPU is working?
>
>To quote "PowerPC Microprocessor Common Hardware Reference Platform: A
>System Architecture", section 12.2.1 - SMP-Safe Boot:
>
>       3. One of the first things that the firmware does is
>          establish one of the processors as the `master'.
>          The `master' is a single processor which continues
>          with the rest of the booting process; all of the
>          others are places in a `stopped state'.  A processor
>          in this `stopped state' is out of the picture; it does
>          nothing that affects the state of the system and will
>          continue to be in that state until awakened by
>          some outside force such as an inter-processor interrupt
>          (IPI).
>
>Jason R. Thorpe                                       
>thorpej%nas.nasa.gov@localhost
>NASA Ames Research Center                               Home: 408.866.1912
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>