Port-hpcarm archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

AW: Jornada 720 with 128MB RAM

It seems that we need to set two CPU control registers: DRAM Configuration
Register MDCNFG (0h A000 0000) and the DRAM Refresh Control Register MDREFR
(0h A000 001C).
In the MDCNFG we have to set DRAC00,DRAC01,DRAC02 to 1,1,0
In the MDREFR we have to set to account 8k of refresh-adresses i think.
I hope someone can explain me in which part of the kernel source code i can
set the CPU control registers or implement code to do that.


-----Ursprüngliche Nachricht-----
Von: port-hpcarm-owner%NetBSD.org@localhost [mailto:port-hpcarm-owner%NetBSD.org@localhost] Im
Auftrag von Robert Swindells
Gesendet: Montag, 21. Oktober 2019 13:11
An: Stefan Lehner
Cc: port-hpcarm%netbsd.org@localhost
Betreff: Re: Jornada 720 with 128MB RAM

"Stefan Lehner" <stefan-lehner%aon.at@localhost> wrote:
>My name ist Stefan, i like to upgrade my Jornada 720 to 128MB RAM. 
>I soldered two Samsung K4S511632C-KC75 RAM Chips instead oft the two old
>16MB ones on to the RAM/ROM board. So the hardware part is done, the
>J720 boots fine into WinCE and with the hpcboot.exe into NetBSD. But as
>expected only with 32MB available.

The first thing that I would check is whether the required timings
for the new RAM chips are different to the old ones.

Home | Main Index | Thread Index | Old Index