Port-arm archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

Re: VM-friendly 64-bit ARM binaries that use Linux bootloader & VirtIO support?



I don't see a UART device modeled in the device tree. Is it a PCI device maybe? You should be able to find it in dmesg -- please share.

I guess if there is not a node in the devicetree for the UART we'll have to add some other way to specify it by device name (consdev=com0 or something like that).


On Mon, 30 Nov 2020, Chris Hanson wrote:

On Nov 30, 2020, at 1:35 PM, Chris Hanson <cmhanson%eschatologist.net@localhost> wrote:

On Nov 30, 2020, at 11:43 AM, Jared McNeill <jmcneill%invisible.ca@localhost> wrote:

Is there some way to explore it through /sys/firmware/devicetree? I don't have a Linux Arm box handy to check.

Thanks, I'll give that a shot.

Below is /sys/firmware/devicetree when semi-successfully booting to a linux install environment. I say "semi-successfully" because I get to a shell because the boot can't continue; I haven't figured out the incantation to truly boot Fedora either. (I've heard Ubuntu works, I'm going to try that next.)

 -- Chris

./base
./base/clock
./base/clock/clock-output-names
./base/clock/#clock-cells
./base/clock/clock-frequency
./base/clock/compatible
./base/clock/phandle
./base/clock/name
./base/#address-cells
./base/pci
./base/pci/#address-cells
./base/pci/bus-range
./base/pci/interrupt-map
./base/pci/#size-cells
./base/pci/device_type
./base/pci/interrupt-map-mask
./base/pci/compatible
./base/pci/ranges
./base/pci/#interrupt-cells
./base/pci/reg
./base/pci/name
./base/gic
./base/gic/#address-cells
./base/gic/#size-cells
./base/gic/compatible
./base/gic/ranges
./base/gic/#interrupt-cells
./base/gic/reg
./base/gic/phandle
./base/gic/name
./base/gic/interrupt-controller
./base/psci
./base/psci/method
./base/psci/compatible
./base/psci/cpu_on
./base/psci/migrate
./base/psci/cpu_suspend
./base/psci/name
./base/psci/cpu_off
./base/#size-cells
./base/interrupt-parent
./base/gpio-keys
./base/gpio-keys/power
./base/gpio-keys/power/label
./base/gpio-keys/power/linux,code
./base/gpio-keys/power/name
./base/gpio-keys/power/debounce-interval
./base/gpio-keys/power/gpios
./base/gpio-keys/compatible
./base/gpio-keys/name
./base/timer
./base/timer/always-on
./base/timer/interrupts
./base/timer/compatible
./base/timer/name
./base/pl061
./base/pl061/clock-names
./base/pl061/gpio-controller
./base/pl061/interrupts
./base/pl061/clocks
./base/pl061/compatible
./base/pl061/reg
./base/pl061/phandle
./base/pl061/#gpio-cells
./base/pl061/name
./base/chosen
./base/chosen/linux,initrd-end
./base/chosen/bootargs
./base/chosen/linux,initrd-start
./base/chosen/name
./base/cpus
./base/cpus/cpu@
./base/cpus/cpu@1/device_type
./base/cpus/cpu@1/compatible
./base/cpus/cpu@1/reg
./base/cpus/cpu@1/enable-method
./base/cpus/cpu@1/name
./base/cpus/#address-cells
./base/cpus/#size-cells
./base/cpus/cpu@
./base/cpus/cpu@2/device_type
./base/cpus/cpu@2/compatible
./base/cpus/cpu@2/reg
./base/cpus/cpu@2/enable-method
./base/cpus/cpu@2/name
./base/cpus/cpu@
./base/cpus/cpu@0/device_type
./base/cpus/cpu@0/compatible
./base/cpus/cpu@0/reg
./base/cpus/cpu@0/enable-method
./base/cpus/cpu@0/name
./base/cpus/name
./base/cpus/cpu@
./base/cpus/cpu@3/device_type
./base/cpus/cpu@3/compatible
./base/cpus/cpu@3/reg
./base/cpus/cpu@3/enable-method
./base/cpus/cpu@3/name
./base/name
./base/memory
./base/memory/device_type
./base/memory/reg
./base/memory/name




Home | Main Index | Thread Index | Old Index