Predictable CPU discovery (was: Re: CVS commit: src/sys/arch/aarch64/aarch64)

[Jason Thorpe <thorpej%me.com@localhost>]

Moving to port-arm@.

> On Jul 2, 2020, at 11:37 AM, Jared McNeill <jmcneill%invisible.ca@localhost> wrote:
> 
> I think this will have issues on some big.LITTLE configurations like Rockchip RK3399.
> 
> In the RK3399 case cpu[0-3] is VIPT I$ and cpu[4-5] is PIPT I$. Boot order of secondaries is not guaranteed so it is possible to get different values of aarch64_cache_vindexsize from one boot to the next.

But that could be changed!

The Alpha port, for example, ensures predictable ordering and discovery of CPU properties in a predictable way from boot-to-boot.

It does this by booting the secondaries one at a time as they're discovered in the PCS table, letting them announce their extensions, etc., but then spin waiting to be released.

cpu_boot_secondary_processors() then simply sets a couple of bits to notify the waiting CPUs that they can move ahead.

-- thorpej