Re: Cortex A9 private timer

[Nick Hudson <nick.hudson%gmx.co.uk@localhost>]

On 16/10/2019 19:20, Aymeric Vincent wrote:
> Hi,
>
> the addition of a9ptmr support breaks at least the DE0 Nano SoC port
> (Cortex A9) because both a9tmr and a9ptmr are enabled. The kernel hangs
> during boot in what looks like an interrupt storm but I didn't
> investigate much. A workaround for me is to disable a9ptmr in the dtb
> but I fail to see the intent of making a private timer the one
> reponsible for calling hardclock().

Does the attached patch fix things?

We track mainline Linux DTS so this local change should be reverted.


> So far, we had a9tmr on Cortex A5/A9 and gtmr on other Cortex. They both
> call hardclock() and don't collide because no SoC can provide both so
> only one will attach at runtime.
>
> I see that the meson platform mandates the use of a9ptmr_delay, so there
> is certainly a reason for this support but it breaks other ports and was
> pulled up to netbsd-9 very quickly... :-/ May I ask for a little
> explanation?


Sorry for the breakage.

Hopefully the diff fixes things.

Nick

Index: sys/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts,v
retrieving revision 1.2
diff -u -p -u -r1.2 socfpga_cyclone5_de0_nano_soc.dts
--- sys/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts	22 Jan 2019 15:30:57 -0000	1.2
+++ sys/arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts	17 Oct 2019 15:10:05 -0000
@@ -4,12 +4,6 @@
 
 / {
 	soc {
-		gtimer@fffec200 {
-			compatible = "arm,cortex-a9-global-timer";
-			reg = <0xfffec200 0x20>;
-			clocks = <&mpu_periph_clk>;
-			interrupts = <1 11 0x301>;
-		};
 		usb@ffb40000 {
 			dr_mode = "host";
 		};