Hi,
the DE0 nano soc refuses to boot since it has been switched to an EFI
boot. The reason is that the L2 cache is used by u-boot in EFI mode and
remains active when the kernel is launched. This results in random
chunks of 32 bytes to contain random code, notably in the kernel.
I suspect at least any Cortex A9(/A5?) platform will have this problem.
The following quick and dirty patch in sys/arch/arm/arm/armv6_start.S
makes the kernel boot for me from EFI. However, the 0xfffef000 base
address is Cyclone V specific and at this point in the boot process, we
haven't yet decided which platform we run on.
Is there an EFI way to flush and disable the L2 cache or do we need to
find another way around?
Regards,
Aymeric
tst r0, #CPU_CONTROL_DC_ENABLE
blne armv7_dcache_wbinv_all
+ movw r1, #:lower16:0xfffef000
+ movt r1, #:upper16:0xfffef000
+ mov r2, #0x1
+ ldr r0, [r1, #0x100]
+ tst r0, r2
+ beq 1f
+
+ mov r2, #0xff
+ str r2, [r1, #0x7fc] // flush and inval all ways
+2:
+ ldr r0, [r1, #0x7fc] // wait for completion
+ tst r0, r2
+ bne 2b
+
+ ldr r0, [r1, #0x100] // disable L2$
+ mov r2, #0x1
+ bic r0, r2
+ str r0, [r1, #0x100]
+1:
+
// TeX remap
#define ARMV7_SCTLR_CLEAR ( \