On Sat, 20 Apr 2019, Jared McNeill wrote:
On Sat, 20 Apr 2019, Izumi Tsutsui wrote:
SWP and SWPB instructions have been deperecated on ARMv6 and
removed since ARMv7 (because atomic LDREX and STREX insns are added).
FYI some ARMv7 implementations still support it - see SW (bit 10) bit
of SCTLR on Cortex-A7. Unfortunately, there is no SW bit on Cortex-A53
so you are out of luck on RPI3.
This looks like a bug (grr ifdefs):
https://nxr.netbsd.org/xref/src/sys/arch/arm/cortex/a9_mpsubr.S#140
So a Cortex-A7 board running the RPI2 kernel should work. The same board
running the GENERIC kernel will fail though...