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Re: Support for trees of clocks served by one clock manager
Jared McNeill <jmcneill%invisible.ca@localhost> writes:
> Can you share your dts? Searching up the tree for clock controllers is
> not specified in the clock-bindings documentation afaict.
Sure, the clock tree is in
sys/external/gpl2/dts/dist/arch/arm/boot/dts/socfpga.dtsi
and I include below a dump of the exact dtb I use for completeness.
In the case I'm interested in, nothing at the level of a peripheral will
mention the phandle of the "clkmgr": each peripheral points to its
clock, and the clocks never mention their clock manager: most are simply
grand-children of it and that's the link. But we need to find the clock
manager in order to invoke the decoding method.
In order to avoid the loop, I could register all clocks as clock
managers but that's _very_ ugly (it works).
> As far as decode is concerned, it was a mistake on my part not to
> include phandle as a separate parameter. I would rather fix it that
> way, along with making sure that the various decode/acquire callbacks
> in fdtbus are consistent here.
Sure, I'm fine with including the clock phandle as an explicit
parameter. My patch actually covered two issues.
Regards,
Aymeric
/dts-v1/;
/memreserve/ 0x0000000000000000 0x0000000000001000;
/ {
#address-cells = <0x1>;
#size-cells = <0x1>;
model = "Terasic DE-0(Atlas)";
compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
aliases {
ethernet0 = "/soc/ethernet@ff702000";
ethernet1 = "/soc/ethernet@ff702000";
serial0 = "/soc/serial0@ffc02000";
serial1 = "/soc/serial1@ffc03000";
timer0 = "/soc/timer0@ffc08000";
timer1 = "/soc/timer1@ffc09000";
timer2 = "/soc/timer2@ffd00000";
timer3 = "/soc/timer3@ffd01000";
};
cpus {
#address-cells = <0x1>;
#size-cells = <0x0>;
enable-method = "altr,socfpga-smp";
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
next-level-cache = <0x1>;
linux,phandle = <0x3>;
phandle = <0x3>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x1>;
next-level-cache = <0x1>;
linux,phandle = <0x4>;
phandle = <0x4>;
};
};
pmu@ff111000 {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <0x2>;
interrupts = <0x0 0xb0 0x4 0x0 0xb1 0x4>;
interrupt-affinity = <0x3 0x4>;
reg = <0xff111000 0x1000 0xff113000 0x1000>;
linux,phandle = <0x36>;
phandle = <0x36>;
};
intc@fffed000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <0x3>;
interrupt-controller;
reg = <0xfffed000 0x1000 0xfffec100 0x100>;
linux,phandle = <0x2>;
phandle = <0x2>;
};
soc {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "simple-bus";
device_type = "soc";
interrupt-parent = <0x2>;
ranges;
amba {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
pdma@ffe01000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xffe01000 0x1000>;
interrupts = <0x0 0x68 0x4 0x0 0x69 0x4 0x0 0x6a 0x4 0x0 0x6b 0x4 0x0 0x6c 0x4 0x0 0x6d 0x4 0x0 0x6e 0x4 0x0 0x6f 0x4>;
#dma-cells = <0x1>;
#dma-channels = <0x8>;
#dma-requests = <0x20>;
clocks = <0x5>;
clock-names = "apb_pclk";
linux,phandle = <0x32>;
phandle = <0x32>;
};
};
base_fpga_region {
compatible = "fpga-region";
fpga-mgr = <0x6>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
can@ffc00000 {
compatible = "bosch,d_can";
reg = <0xffc00000 0x1000>;
interrupts = <0x0 0x83 0x4 0x0 0x84 0x4 0x0 0x85 0x4 0x0 0x86 0x4>;
clocks = <0x7>;
status = "disabled";
linux,phandle = <0x37>;
phandle = <0x37>;
};
can@ffc01000 {
compatible = "bosch,d_can";
reg = <0xffc01000 0x1000>;
interrupts = <0x0 0x87 0x4 0x0 0x88 0x4 0x0 0x89 0x4 0x0 0x8a 0x4>;
clocks = <0x8>;
status = "disabled";
linux,phandle = <0x38>;
phandle = <0x38>;
};
clkmgr@ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
clocks {
#address-cells = <0x1>;
#size-cells = <0x0>;
osc1 {
#clock-cells = <0x0>;
compatible = "fixed-clock";
clock-frequency = <0x17d7840>;
linux,phandle = <0x9>;
phandle = <0x9>;
};
osc2 {
#clock-cells = <0x0>;
compatible = "fixed-clock";
linux,phandle = <0xb>;
phandle = <0xb>;
};
f2s_periph_ref_clk {
#clock-cells = <0x0>;
compatible = "fixed-clock";
linux,phandle = <0xc>;
phandle = <0xc>;
};
f2s_sdram_ref_clk {
#clock-cells = <0x0>;
compatible = "fixed-clock";
linux,phandle = <0xe>;
phandle = <0xe>;
};
main_pll@40 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x0>;
compatible = "altr,socfpga-pll-clock";
clocks = <0x9>;
reg = <0x40>;
linux,phandle = <0xa>;
phandle = <0xa>;
mpuclk@48 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xa>;
div-reg = <0xe0 0x0 0x9>;
reg = <0x48>;
linux,phandle = <0x10>;
phandle = <0x10>;
};
mainclk@4c {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xa>;
div-reg = <0xe4 0x0 0x9>;
reg = <0x4c>;
linux,phandle = <0x11>;
phandle = <0x11>;
};
dbg_base_clk@50 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xa 0x9>;
div-reg = <0xe8 0x0 0x9>;
reg = <0x50>;
linux,phandle = <0x14>;
phandle = <0x14>;
};
main_qspi_clk@54 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xa>;
reg = <0x54>;
linux,phandle = <0x1d>;
phandle = <0x1d>;
};
main_nand_sdmmc_clk@58 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xa>;
reg = <0x58>;
linux,phandle = <0x1a>;
phandle = <0x1a>;
};
cfg_h2f_usr0_clk@5c {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xa>;
reg = <0x5c>;
linux,phandle = <0x16>;
phandle = <0x16>;
};
};
periph_pll@80 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x0>;
compatible = "altr,socfpga-pll-clock";
clocks = <0x9 0xb 0xc>;
reg = <0x80>;
linux,phandle = <0xd>;
phandle = <0xd>;
emac0_clk@88 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xd>;
reg = <0x88>;
linux,phandle = <0x17>;
phandle = <0x17>;
};
emac1_clk@8c {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xd>;
reg = <0x8c>;
linux,phandle = <0x18>;
phandle = <0x18>;
};
per_qsi_clk@90 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xd>;
reg = <0x90>;
linux,phandle = <0x1e>;
phandle = <0x1e>;
};
per_nand_mmc_clk@94 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xd>;
reg = <0x94>;
linux,phandle = <0x1b>;
phandle = <0x1b>;
};
per_base_clk@98 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xd>;
reg = <0x98>;
linux,phandle = <0x13>;
phandle = <0x13>;
};
h2f_usr1_clk@9c {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xd>;
reg = <0x9c>;
linux,phandle = <0x19>;
phandle = <0x19>;
};
};
sdram_pll@c0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x0>;
compatible = "altr,socfpga-pll-clock";
clocks = <0x9 0xb 0xe>;
reg = <0xc0>;
linux,phandle = <0xf>;
phandle = <0xf>;
ddr_dqs_clk@c8 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xf>;
reg = <0xc8>;
linux,phandle = <0x1f>;
phandle = <0x1f>;
};
ddr_2x_dqs_clk@cc {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xf>;
reg = <0xcc>;
linux,phandle = <0x20>;
phandle = <0x20>;
};
ddr_dq_clk@d0 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xf>;
reg = <0xd0>;
linux,phandle = <0x21>;
phandle = <0x21>;
};
h2f_usr2_clk@d4 {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0xf>;
reg = <0xd4>;
linux,phandle = <0x22>;
phandle = <0x22>;
};
};
mpu_periph_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0x10>;
fixed-divider = <0x4>;
linux,phandle = <0x31>;
phandle = <0x31>;
};
mpu_l2_ram_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0x10>;
fixed-divider = <0x2>;
linux,phandle = <0x39>;
phandle = <0x39>;
};
l4_main_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x11>;
clk-gate = <0x60 0x0>;
linux,phandle = <0x5>;
phandle = <0x5>;
};
l3_main_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-perip-clk";
clocks = <0x11>;
fixed-divider = <0x1>;
linux,phandle = <0x3a>;
phandle = <0x3a>;
};
l3_mp_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x11>;
div-reg = <0x64 0x0 0x2>;
clk-gate = <0x60 0x1>;
linux,phandle = <0x12>;
phandle = <0x12>;
};
l3_sp_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x12>;
div-reg = <0x64 0x2 0x2>;
linux,phandle = <0x3b>;
phandle = <0x3b>;
};
l4_mp_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x11 0x13>;
div-reg = <0x64 0x4 0x3>;
clk-gate = <0x60 0x2>;
linux,phandle = <0x27>;
phandle = <0x27>;
};
l4_sp_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x11 0x13>;
div-reg = <0x64 0x7 0x3>;
clk-gate = <0x60 0x3>;
linux,phandle = <0x28>;
phandle = <0x28>;
};
dbg_at_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x14>;
div-reg = <0x68 0x0 0x2>;
clk-gate = <0x60 0x4>;
linux,phandle = <0x15>;
phandle = <0x15>;
};
dbg_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x15>;
div-reg = <0x68 0x2 0x2>;
clk-gate = <0x60 0x5>;
linux,phandle = <0x3c>;
phandle = <0x3c>;
};
dbg_trace_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x14>;
div-reg = <0x6c 0x0 0x3>;
clk-gate = <0x60 0x6>;
linux,phandle = <0x3d>;
phandle = <0x3d>;
};
dbg_timer_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x14>;
clk-gate = <0x60 0x7>;
linux,phandle = <0x3e>;
phandle = <0x3e>;
};
cfg_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x16>;
clk-gate = <0x60 0x8>;
linux,phandle = <0x3f>;
phandle = <0x3f>;
};
h2f_user0_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x16>;
clk-gate = <0x60 0x9>;
linux,phandle = <0x40>;
phandle = <0x40>;
};
emac_0_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x17>;
clk-gate = <0xa0 0x0>;
linux,phandle = <0x25>;
phandle = <0x25>;
};
emac_1_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x18>;
clk-gate = <0xa0 0x1>;
linux,phandle = <0x26>;
phandle = <0x26>;
};
usb_mp_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x13>;
clk-gate = <0xa0 0x2>;
div-reg = <0xa4 0x0 0x3>;
linux,phandle = <0x33>;
phandle = <0x33>;
};
spi_m_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x13>;
clk-gate = <0xa0 0x3>;
div-reg = <0xa4 0x3 0x3>;
linux,phandle = <0x30>;
phandle = <0x30>;
};
can0_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x13>;
clk-gate = <0xa0 0x4>;
div-reg = <0xa4 0x6 0x3>;
linux,phandle = <0x7>;
phandle = <0x7>;
};
can1_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x13>;
clk-gate = <0xa0 0x5>;
div-reg = <0xa4 0x9 0x3>;
linux,phandle = <0x8>;
phandle = <0x8>;
};
gpio_db_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x13>;
clk-gate = <0xa0 0x6>;
div-reg = <0xa8 0x0 0x18>;
linux,phandle = <0x41>;
phandle = <0x41>;
};
h2f_user1_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x19>;
clk-gate = <0xa0 0x7>;
linux,phandle = <0x42>;
phandle = <0x42>;
};
sdmmc_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0xc 0x1a 0x1b>;
clk-gate = <0xa0 0x8>;
clk-phase = <0x0 0x87>;
linux,phandle = <0x1c>;
phandle = <0x1c>;
};
sdmmc_clk_divided {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x1c>;
clk-gate = <0xa0 0x8>;
fixed-divider = <0x4>;
linux,phandle = <0x2b>;
phandle = <0x2b>;
};
nand_x_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0xc 0x1a 0x1b>;
clk-gate = <0xa0 0x9>;
linux,phandle = <0x43>;
phandle = <0x43>;
};
nand_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0xc 0x1a 0x1b>;
clk-gate = <0xa0 0xa>;
fixed-divider = <0x4>;
linux,phandle = <0x2d>;
phandle = <0x2d>;
};
qspi_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0xc 0x1d 0x1e>;
clk-gate = <0xa0 0xb>;
linux,phandle = <0x2e>;
phandle = <0x2e>;
};
ddr_dqs_clk_gate {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x1f>;
clk-gate = <0xd8 0x0>;
linux,phandle = <0x44>;
phandle = <0x44>;
};
ddr_2x_dqs_clk_gate {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x20>;
clk-gate = <0xd8 0x1>;
linux,phandle = <0x45>;
phandle = <0x45>;
};
ddr_dq_clk_gate {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x21>;
clk-gate = <0xd8 0x2>;
linux,phandle = <0x46>;
phandle = <0x46>;
};
h2f_user2_clk {
#clock-cells = <0x0>;
compatible = "altr,socfpga-gate-clk";
clocks = <0x22>;
clk-gate = <0xd8 0x3>;
linux,phandle = <0x47>;
phandle = <0x47>;
};
};
};
fpga_bridge@ff400000 {
compatible = "altr,socfpga-lwhps2fpga-bridge";
reg = <0xff400000 0x100000>;
resets = <0x23 0x61>;
clocks = <0x5>;
linux,phandle = <0x48>;
phandle = <0x48>;
};
fpga_bridge@ff500000 {
compatible = "altr,socfpga-hps2fpga-bridge";
reg = <0xff500000 0x10000>;
resets = <0x23 0x60>;
clocks = <0x5>;
linux,phandle = <0x49>;
phandle = <0x49>;
};
fpgamgr@ff706000 {
compatible = "altr,socfpga-fpga-mgr";
reg = <0xff706000 0x1000 0xffb90000 0x4>;
interrupts = <0x0 0xaf 0x4>;
linux,phandle = <0x6>;
phandle = <0x6>;
};
ethernet@ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
altr,sysmgr-syscon = <0x24 0x60 0x0>;
reg = <0xff700000 0x2000>;
interrupts = <0x0 0x73 0x4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
clocks = <0x25>;
clock-names = "stmmaceth";
resets = <0x23 0x20>;
reset-names = "stmmaceth";
snps,multicast-filter-bins = <0x100>;
snps,perfect-filter-entries = <0x80>;
tx-fifo-depth = <0x1000>;
rx-fifo-depth = <0x1000>;
status = "disabled";
linux,phandle = <0x4a>;
phandle = <0x4a>;
};
ethernet@ff702000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
altr,sysmgr-syscon = <0x24 0x60 0x2>;
reg = <0xff702000 0x2000>;
interrupts = <0x0 0x78 0x4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];
clocks = <0x26>;
clock-names = "stmmaceth";
resets = <0x23 0x21>;
reset-names = "stmmaceth";
snps,multicast-filter-bins = <0x100>;
snps,perfect-filter-entries = <0x80>;
tx-fifo-depth = <0x1000>;
rx-fifo-depth = <0x1000>;
status = "okay";
phy-mode = "rgmii";
txd0-skew-ps = <0x0>;
txd1-skew-ps = <0x0>;
txd2-skew-ps = <0x0>;
txd3-skew-ps = <0x0>;
rxd0-skew-ps = <0x1a4>;
rxd1-skew-ps = <0x1a4>;
rxd2-skew-ps = <0x1a4>;
rxd3-skew-ps = <0x1a4>;
txen-skew-ps = <0x0>;
txc-skew-ps = <0x744>;
rxdv-skew-ps = <0x1a4>;
rxc-skew-ps = <0x690>;
max-frame-size = <0xed8>;
linux,phandle = <0x4b>;
phandle = <0x4b>;
};
gpio@ff708000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,dw-apb-gpio";
reg = <0xff708000 0x1000>;
clocks = <0x27>;
status = "okay";
linux,phandle = <0x4c>;
phandle = <0x4c>;
gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <0x2>;
snps,nr-gpios = <0x1d>;
reg = <0x0>;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupts = <0x0 0xa4 0x4>;
linux,phandle = <0x4d>;
phandle = <0x4d>;
};
};
gpio@ff709000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,dw-apb-gpio";
reg = <0xff709000 0x1000>;
clocks = <0x27>;
status = "okay";
linux,phandle = <0x4e>;
phandle = <0x4e>;
gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <0x2>;
snps,nr-gpios = <0x1d>;
reg = <0x0>;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupts = <0x0 0xa5 0x4>;
linux,phandle = <0x35>;
phandle = <0x35>;
};
};
gpio@ff70a000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,dw-apb-gpio";
reg = <0xff70a000 0x1000>;
clocks = <0x27>;
status = "okay";
linux,phandle = <0x4f>;
phandle = <0x4f>;
gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <0x2>;
snps,nr-gpios = <0x1b>;
reg = <0x0>;
interrupt-controller;
#interrupt-cells = <0x2>;
interrupts = <0x0 0xa6 0x4>;
linux,phandle = <0x29>;
phandle = <0x29>;
};
};
i2c@ffc04000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,designware-i2c";
reg = <0xffc04000 0x1000>;
resets = <0x23 0x2c>;
clocks = <0x28>;
interrupts = <0x0 0x9e 0x4>;
status = "okay";
clock-frequency = <0x186a0>;
linux,phandle = <0x50>;
phandle = <0x50>;
adxl345@0 {
compatible = "adi,adxl345";
reg = <0x53>;
interrupt-parent = <0x29>;
interrupts = <0x3 0x2>;
linux,phandle = <0x51>;
phandle = <0x51>;
};
};
i2c@ffc05000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,designware-i2c";
reg = <0xffc05000 0x1000>;
resets = <0x23 0x2d>;
clocks = <0x28>;
interrupts = <0x0 0x9f 0x4>;
status = "disabled";
linux,phandle = <0x52>;
phandle = <0x52>;
};
i2c@ffc06000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,designware-i2c";
reg = <0xffc06000 0x1000>;
resets = <0x23 0x2e>;
clocks = <0x28>;
interrupts = <0x0 0xa0 0x4>;
status = "disabled";
linux,phandle = <0x53>;
phandle = <0x53>;
};
i2c@ffc07000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "snps,designware-i2c";
reg = <0xffc07000 0x1000>;
resets = <0x23 0x2f>;
clocks = <0x28>;
interrupts = <0x0 0xa1 0x4>;
status = "disabled";
linux,phandle = <0x54>;
phandle = <0x54>;
};
eccmgr {
compatible = "altr,socfpga-ecc-manager";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
linux,phandle = <0x55>;
phandle = <0x55>;
l2-ecc@ffd08140 {
compatible = "altr,socfpga-l2-ecc";
reg = <0xffd08140 0x4>;
interrupts = <0x0 0x24 0x1 0x0 0x25 0x1>;
};
ocram-ecc@ffd08144 {
compatible = "altr,socfpga-ocram-ecc";
reg = <0xffd08144 0x4>;
iram = <0x2a>;
interrupts = <0x0 0xb2 0x1 0x0 0xb3 0x1>;
};
};
l2-cache@fffef000 {
compatible = "arm,pl310-cache";
reg = <0xfffef000 0x1000>;
interrupts = <0x0 0x26 0x4>;
cache-unified;
cache-level = <0x2>;
arm,tag-latency = <0x1 0x1 0x1>;
arm,data-latency = <0x2 0x1 0x1>;
prefetch-data = <0x1>;
prefetch-instr = <0x1>;
arm,shared-override;
arm,double-linefill = <0x1>;
arm,double-linefill-incr = <0x0>;
arm,double-linefill-wrap = <0x1>;
arm,prefetch-drop = <0x0>;
arm,prefetch-offset = <0x7>;
linux,phandle = <0x1>;
phandle = <0x1>;
};
l3regs@0xff800000 {
compatible = "altr,l3regs", "syscon";
reg = <0xff800000 0x1000>;
};
dwmmc0@ff704000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>;
interrupts = <0x0 0x8b 0x4>;
fifo-depth = <0x400>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clocks = <0x27 0x2b>;
clock-names = "biu", "ciu";
status = "okay";
broken-cd;
bus-width = <0x4>;
cap-mmc-highspeed;
cap-sd-highspeed;
vmmc-supply = <0x2c>;
vqmmc-supply = <0x2c>;
linux,phandle = <0x56>;
phandle = <0x56>;
};
nand@ff900000 {
#address-cells = <0x1>;
#size-cells = <0x1>;
compatible = "denali,denali-nand-dt";
reg = <0xff900000 0x100000 0xffb80000 0x10000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0x0 0x90 0x4>;
dma-mask = <0xffffffff>;
clocks = <0x2d>;
status = "disabled";
linux,phandle = <0x57>;
phandle = <0x57>;
};
sram@ffff0000 {
compatible = "mmio-sram";
reg = <0xffff0000 0x10000>;
linux,phandle = <0x2a>;
phandle = <0x2a>;
};
spi@ff705000 {
compatible = "cdns,qspi-nor";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0xff705000 0x1000 0xffa00000 0x1000>;
interrupts = <0x0 0x97 0x4>;
cdns,fifo-depth = <0x80>;
cdns,fifo-width = <0x4>;
cdns,trigger-address = <0x0>;
clocks = <0x2e>;
status = "disabled";
linux,phandle = <0x58>;
phandle = <0x58>;
};
rstmgr@ffd05000 {
#reset-cells = <0x1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
altr,modrst-offset = <0x10>;
linux,phandle = <0x23>;
phandle = <0x23>;
};
snoop-control-unit@fffec000 {
compatible = "arm,cortex-a9-scu";
reg = <0xfffec000 0x100>;
linux,phandle = <0x59>;
phandle = <0x59>;
};
sdr@ffc25000 {
compatible = "altr,sdr-ctl", "syscon";
reg = <0xffc25000 0x1000>;
linux,phandle = <0x2f>;
phandle = <0x2f>;
};
sdramedac {
compatible = "altr,sdram-edac";
altr,sdr-syscon = <0x2f>;
interrupts = <0x0 0x27 0x4>;
};
spi@fff00000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0xfff00000 0x1000>;
interrupts = <0x0 0x9a 0x4>;
num-cs = <0x4>;
clocks = <0x30>;
status = "disabled";
linux,phandle = <0x5a>;
phandle = <0x5a>;
};
spi@fff01000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0xfff01000 0x1000>;
interrupts = <0x0 0x9b 0x4>;
num-cs = <0x4>;
clocks = <0x30>;
status = "disabled";
linux,phandle = <0x5b>;
phandle = <0x5b>;
};
sysmgr@ffd08000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd08000 0x4000>;
cpu1-start-addr = <0xffd080c4>;
linux,phandle = <0x24>;
phandle = <0x24>;
};
timer@fffec600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xfffec600 0x100>;
interrupts = <0x1 0xd 0xf01>;
clocks = <0x31>;
};
timer0@ffc08000 {
compatible = "snps,dw-apb-timer";
interrupts = <0x0 0xa7 0x4>;
reg = <0xffc08000 0x1000>;
clocks = <0x28>;
clock-names = "timer";
linux,phandle = <0x5c>;
phandle = <0x5c>;
};
timer1@ffc09000 {
compatible = "snps,dw-apb-timer";
interrupts = <0x0 0xa8 0x4>;
reg = <0xffc09000 0x1000>;
clocks = <0x28>;
clock-names = "timer";
linux,phandle = <0x5d>;
phandle = <0x5d>;
};
timer2@ffd00000 {
compatible = "snps,dw-apb-timer";
interrupts = <0x0 0xa9 0x4>;
reg = <0xffd00000 0x1000>;
clocks = <0x9>;
clock-names = "timer";
linux,phandle = <0x5e>;
phandle = <0x5e>;
};
timer3@ffd01000 {
compatible = "snps,dw-apb-timer";
interrupts = <0x0 0xaa 0x4>;
reg = <0xffd01000 0x1000>;
clocks = <0x9>;
clock-names = "timer";
linux,phandle = <0x5f>;
phandle = <0x5f>;
};
serial0@ffc02000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02000 0x1000>;
interrupts = <0x0 0xa2 0x4>;
reg-shift = <0x2>;
reg-io-width = <0x4>;
clocks = <0x28>;
dmas = <0x32 0x1c 0x32 0x1d>;
dma-names = "tx", "rx";
status = "okay";
linux,phandle = <0x60>;
phandle = <0x60>;
};
serial1@ffc03000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc03000 0x1000>;
interrupts = <0x0 0xa3 0x4>;
reg-shift = <0x2>;
reg-io-width = <0x4>;
clocks = <0x28>;
dmas = <0x32 0x1e 0x32 0x1f>;
dma-names = "tx", "rx";
linux,phandle = <0x61>;
phandle = <0x61>;
};
usbphy {
#phy-cells = <0x0>;
compatible = "usb-nop-xceiv";
status = "okay";
linux,phandle = <0x34>;
phandle = <0x34>;
};
usb@ffb00000 {
compatible = "snps,dwc2";
reg = <0xffb00000 0xffff>;
interrupts = <0x0 0x7d 0x4>;
clocks = <0x33>;
clock-names = "otg";
resets = <0x23 0x22>;
reset-names = "dwc2";
phys = <0x34>;
phy-names = "usb2-phy";
status = "disabled";
linux,phandle = <0x62>;
phandle = <0x62>;
};
usb@ffb40000 {
compatible = "snps,dwc2";
reg = <0xffb40000 0xffff>;
interrupts = <0x0 0x80 0x4>;
clocks = <0x33>;
clock-names = "otg";
resets = <0x23 0x23>;
reset-names = "dwc2";
phys = <0x34>;
phy-names = "usb2-phy";
status = "okay";
dr_mode = "host";
linux,phandle = <0x63>;
phandle = <0x63>;
};
watchdog@ffd02000 {
compatible = "snps,dw-wdt";
reg = <0xffd02000 0x1000>;
interrupts = <0x0 0xab 0x4>;
clocks = <0x9>;
status = "okay";
linux,phandle = <0x64>;
phandle = <0x64>;
};
watchdog@ffd03000 {
compatible = "snps,dw-wdt";
reg = <0xffd03000 0x1000>;
interrupts = <0x0 0xac 0x4>;
clocks = <0x9>;
status = "disabled";
linux,phandle = <0x65>;
phandle = <0x65>;
};
gtimer@fffec200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xfffec200 0x20>;
clocks = <0x31>;
interrupts = <0x1 0xb 0x301>;
};
};
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
3-3-v-regulator {
compatible = "regulator-fixed";
regulator-name = "3.3V";
regulator-min-microvolt = <0x325aa0>;
regulator-max-microvolt = <0x325aa0>;
linux,phandle = <0x2c>;
phandle = <0x2c>;
};
leds {
compatible = "gpio-leds";
hps0 {
label = "hps_led0";
gpios = <0x35 0x18 0x0>;
linux,default-trigger = "heartbeat";
};
};
__symbols__ {
cpu0 = "/cpus/cpu@0";
cpu1 = "/cpus/cpu@1";
pmu = "/pmu@ff111000";
intc = "/intc@fffed000";
pdma = "/soc/amba/pdma@ffe01000";
can0 = "/soc/can@ffc00000";
can1 = "/soc/can@ffc01000";
osc1 = "/soc/clkmgr@ffd04000/clocks/osc1";
osc2 = "/soc/clkmgr@ffd04000/clocks/osc2";
f2s_periph_ref_clk = "/soc/clkmgr@ffd04000/clocks/f2s_periph_ref_clk";
f2s_sdram_ref_clk = "/soc/clkmgr@ffd04000/clocks/f2s_sdram_ref_clk";
main_pll = "/soc/clkmgr@ffd04000/clocks/main_pll@40";
mpuclk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/mpuclk@48";
mainclk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/mainclk@4c";
dbg_base_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/dbg_base_clk@50";
main_qspi_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/main_qspi_clk@54";
main_nand_sdmmc_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/main_nand_sdmmc_clk@58";
cfg_h2f_usr0_clk = "/soc/clkmgr@ffd04000/clocks/main_pll@40/cfg_h2f_usr0_clk@5c";
periph_pll = "/soc/clkmgr@ffd04000/clocks/periph_pll@80";
emac0_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@80/emac0_clk@88";
emac1_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@80/emac1_clk@8c";
per_qspi_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@80/per_qsi_clk@90";
per_nand_mmc_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@80/per_nand_mmc_clk@94";
per_base_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@80/per_base_clk@98";
h2f_usr1_clk = "/soc/clkmgr@ffd04000/clocks/periph_pll@80/h2f_usr1_clk@9c";
sdram_pll = "/soc/clkmgr@ffd04000/clocks/sdram_pll@c0";
ddr_dqs_clk = "/soc/clkmgr@ffd04000/clocks/sdram_pll@c0/ddr_dqs_clk@c8";
ddr_2x_dqs_clk = "/soc/clkmgr@ffd04000/clocks/sdram_pll@c0/ddr_2x_dqs_clk@cc";
ddr_dq_clk = "/soc/clkmgr@ffd04000/clocks/sdram_pll@c0/ddr_dq_clk@d0";
h2f_usr2_clk = "/soc/clkmgr@ffd04000/clocks/sdram_pll@c0/h2f_usr2_clk@d4";
mpu_periph_clk = "/soc/clkmgr@ffd04000/clocks/mpu_periph_clk";
mpu_l2_ram_clk = "/soc/clkmgr@ffd04000/clocks/mpu_l2_ram_clk";
l4_main_clk = "/soc/clkmgr@ffd04000/clocks/l4_main_clk";
l3_main_clk = "/soc/clkmgr@ffd04000/clocks/l3_main_clk";
l3_mp_clk = "/soc/clkmgr@ffd04000/clocks/l3_mp_clk";
l3_sp_clk = "/soc/clkmgr@ffd04000/clocks/l3_sp_clk";
l4_mp_clk = "/soc/clkmgr@ffd04000/clocks/l4_mp_clk";
l4_sp_clk = "/soc/clkmgr@ffd04000/clocks/l4_sp_clk";
dbg_at_clk = "/soc/clkmgr@ffd04000/clocks/dbg_at_clk";
dbg_clk = "/soc/clkmgr@ffd04000/clocks/dbg_clk";
dbg_trace_clk = "/soc/clkmgr@ffd04000/clocks/dbg_trace_clk";
dbg_timer_clk = "/soc/clkmgr@ffd04000/clocks/dbg_timer_clk";
cfg_clk = "/soc/clkmgr@ffd04000/clocks/cfg_clk";
h2f_user0_clk = "/soc/clkmgr@ffd04000/clocks/h2f_user0_clk";
emac_0_clk = "/soc/clkmgr@ffd04000/clocks/emac_0_clk";
emac_1_clk = "/soc/clkmgr@ffd04000/clocks/emac_1_clk";
usb_mp_clk = "/soc/clkmgr@ffd04000/clocks/usb_mp_clk";
spi_m_clk = "/soc/clkmgr@ffd04000/clocks/spi_m_clk";
can0_clk = "/soc/clkmgr@ffd04000/clocks/can0_clk";
can1_clk = "/soc/clkmgr@ffd04000/clocks/can1_clk";
gpio_db_clk = "/soc/clkmgr@ffd04000/clocks/gpio_db_clk";
h2f_user1_clk = "/soc/clkmgr@ffd04000/clocks/h2f_user1_clk";
sdmmc_clk = "/soc/clkmgr@ffd04000/clocks/sdmmc_clk";
sdmmc_clk_divided = "/soc/clkmgr@ffd04000/clocks/sdmmc_clk_divided";
nand_x_clk = "/soc/clkmgr@ffd04000/clocks/nand_x_clk";
nand_clk = "/soc/clkmgr@ffd04000/clocks/nand_clk";
qspi_clk = "/soc/clkmgr@ffd04000/clocks/qspi_clk";
ddr_dqs_clk_gate = "/soc/clkmgr@ffd04000/clocks/ddr_dqs_clk_gate";
ddr_2x_dqs_clk_gate = "/soc/clkmgr@ffd04000/clocks/ddr_2x_dqs_clk_gate";
ddr_dq_clk_gate = "/soc/clkmgr@ffd04000/clocks/ddr_dq_clk_gate";
h2f_user2_clk = "/soc/clkmgr@ffd04000/clocks/h2f_user2_clk";
fpga_bridge0 = "/soc/fpga_bridge@ff400000";
fpga_bridge1 = "/soc/fpga_bridge@ff500000";
fpgamgr0 = "/soc/fpgamgr@ff706000";
gmac0 = "/soc/ethernet@ff700000";
gmac1 = "/soc/ethernet@ff702000";
gpio0 = "/soc/gpio@ff708000";
porta = "/soc/gpio@ff708000/gpio-controller@0";
gpio1 = "/soc/gpio@ff709000";
portb = "/soc/gpio@ff709000/gpio-controller@0";
gpio2 = "/soc/gpio@ff70a000";
portc = "/soc/gpio@ff70a000/gpio-controller@0";
i2c0 = "/soc/i2c@ffc04000";
adxl345 = "/soc/i2c@ffc04000/adxl345@0";
i2c1 = "/soc/i2c@ffc05000";
i2c2 = "/soc/i2c@ffc06000";
i2c3 = "/soc/i2c@ffc07000";
eccmgr = "/soc/eccmgr";
L2 = "/soc/l2-cache@fffef000";
mmc0 = "/soc/dwmmc0@ff704000";
mmc = "/soc/dwmmc0@ff704000";
nand0 = "/soc/nand@ff900000";
ocram = "/soc/sram@ffff0000";
qspi = "/soc/spi@ff705000";
rst = "/soc/rstmgr@ffd05000";
scu = "/soc/snoop-control-unit@fffec000";
sdr = "/soc/sdr@ffc25000";
spi0 = "/soc/spi@fff00000";
spi1 = "/soc/spi@fff01000";
sysmgr = "/soc/sysmgr@ffd08000";
timer0 = "/soc/timer0@ffc08000";
timer1 = "/soc/timer1@ffc09000";
timer2 = "/soc/timer2@ffd00000";
timer3 = "/soc/timer3@ffd01000";
uart0 = "/soc/serial0@ffc02000";
uart1 = "/soc/serial1@ffc03000";
usbphy0 = "/soc/usbphy";
usb0 = "/soc/usb@ffb00000";
usb1 = "/soc/usb@ffb40000";
watchdog0 = "/soc/watchdog@ffd02000";
watchdog1 = "/soc/watchdog@ffd03000";
regulator_3_3v = "/3-3-v-regulator";
};
};
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