Re: Deciphering GPIO on Raspberry Pi B+

[Jared McNeill <jmcneill%invisible.ca@localhost>]

On Sat, 14 Apr 2018, Jason Thorpe wrote:

> So, can I assume that the only reason this is broken up into 2 separate “gpio” instances is because the GPIO subsystem can’t handle more than 32 pins on a single controller?

No problem attaching more than 32 pins per GPIO instance.

The old approach was to attach a gpio instance per bank. This makes it 
easier to find things (assuming you print the bank information at attach 
time) especially if you don't have an equal number of pins per bank, at 
the expense of having tonnes of gpio device nodes. The NVIDIA Tegra port 
looks like this:

  tegragpio0 at fdt0: GPIO
  gpio0 at tegragpio0 (A): 8 pins
  gpio1 at tegragpio0 (B): 8 pins
  gpio2 at tegragpio0 (C): 8 pins
  ...
  gpio30 at tegragpio0 (EE): 8 pins


The new approach (I can't remember if this code made it to -8 or not) is 
to expose all pins on a single gpio instance, and to have the controller 
provide an alias for the pin. So on the Allwinner sunxi port you can refer 
to a pin by "PA7" or "PG4" instead of trying to figure out the raw pin 
index.

https://nxr.netbsd.org/xref/src/sys/arch/arm/sunxi/sunxi_gpio.c#785


Cheers,
Jared