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Re: (Ab?)use of MII
On Sun, Apr 05, 2015 at 06:34:12PM +0200, Wolfgang Solfrank wrote:
> so I've got NetBSD running on my Banana Pi BPi-R1.
> With this board, the gigabit net interface on the processor chip is
> connected via mii to a switch chip (BCM 53125). The 5 external ports
> of this chip all have their own phys and are brought out for external
This is an RMII configuration, right, not normal MII?
> With an unmodified BPI kernel, the mii attach code finds all of those
> phys via the mii bus of the processor's ethernet interface and then
> enables only one of those.
That seems exceedingly odd. I don't know this particular switch chip,
but, usually, in this kind of reverse-MII setup, the switch chip provides
one MII per port (or one quad-MII per 4 ports, using quad PHYs, but those
look logically like 4 MIIs except for a minimal set of shared PHY registers)
and the CPU is hooked up just like the PHYs for the physical ports.
I have not seen all the MIIs bridged together as you describe. Is there a
different mode for the switch in which it doesn't do this? I am reasonably
familiar with the Marvell switch parts and a few others; not so much the
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