Re: fix for mirabox(armada370)

[Matt Thomas <matt%3am-software.com@localhost>]

> On Mar 26, 2015, at 12:22 AM, SUENAGA Hiroki <hsuenaga%netbsd.org@localhost> wrote:
> 
> Hi,
> 
> I found two bugs in -current. one of them may fix a issue
> of NSLU2 reported by Eddy.
> 
> can I commit the fix?
> 
> a) tlb_invalidate_asids() not worked on old processors.
> 
> the function allways use armreg_tlbiasidis_write(), but
> old core(non MULTIPROCESSOR capable) doesn't support
> the operation. we need to use armreg_tlbiasid_write()
> instead. patch for arm32_tlb.c is attached.
> 
> this patch may fix a issue of NSLU2. due to TLB Entry
> isn't cleared, userland processes possibly access to
> incorrect physical page and causes mysterious crash.

Since the nSLU2 doesn't use arm32_tlb.c that seems unlikely.

> I confirmed my MIRABOX(ARMADA 370) works fine after
> applying this patch.

That's ok.  Wonder why my MIRABOX worked without this change.

> b) incorrect register usage in pj4b_settb().
> 
> this seems to be just a typo. entry is modified on r2,
> but the code load r0 to TTBR0/1. a patch for
> cpufunc_asm_pj4b.S is attached.

Is cpufunc_asm_pj4b.S really needed.  I've patched it to use 
cpufuncs_armv7 and the mirabox runs fine.  If the pb4b is
really armv7, then asm_pj4b is just redundant.

> Thank you,
> 
> --- a/sys/arch/arm/arm32/arm32_tlb.c
> +++ b/sys/arch/arm/arm32/arm32_tlb.c
> @@ -93,11 +93,19 @@ tlb_invalidate_asids(tlb_asid_t lo, tlb_asid_t hi)
>        arm_dsb();
>        if (arm_has_tlbiasid_p) {
>                for (; lo <= hi; lo++) {
> +#ifdef MULTIPROCESSOR
>                        armreg_tlbiasidis_write(lo);
> +#else
> +                       armreg_tlbiasid_write(lo);
> +#endif
>                }
>                arm_isb();
>                if (__predict_false(vivt_icache_p)) {
> +#ifdef MULTIPROCESSOR
>                        armreg_icialluis_write(0);
> +#else
> +                       armreg_iciallu_write(0);
> +#endif
>                }
>        } else {
>                armreg_tlbiall_write(0);
> --- a/sys/arch/arm/arm/cpufunc_asm_pj4b.S
> +++ b/sys/arch/arm/arm/cpufunc_asm_pj4b.S
> @@ -58,10 +58,10 @@ ENTRY(pj4b_setttb)
> #else
>        bic     r2, r0, #0x18
> #endif
> -       mcr     p15, 0, r0, c2, c0, 0   /* load TTBR0 */
> +       mcr     p15, 0, r2, c2, c0, 0   /* load TTBR0 */
> #ifdef ARM_MMU_EXTENDED
>        cmp     r1, #0
> -       mcreq   p15, 0, r0, c2, c0, 1   /* load TTBR1 */
> +       mcreq   p15, 0, r2, c2, c0, 1   /* load TTBR1 */
> #else
>        mov     r0, #0
>        mcr     p15, 0, r0, c8, c7, 0   /* invalidate I+D TLBs */

It's OK but see above.