Re: TLS register access trapping failure on Orion

["Jonathan A. Kollasch" <jakllsch%kollasch.net@localhost>]

On Sat, Feb 11, 2012 at 12:23:35PM -0800, Matt Thomas wrote:
> 
> On Feb 11, 2012, at 9:26 AM, Jonathan A. Kollasch wrote:
> 
> > On Sat, Feb 11, 2012 at 06:19:20PM +0100, Martin Husemann wrote:
> >> On Sat, Feb 11, 2012 at 10:52:06AM -0600, Jonathan A. Kollasch wrote:
> >>> 
> >>> I'm running a recent -current evbarm on my Marvell Orion box (HP MV2120).
> >> 
> >> What is the exact cpu type?
> > 
> > cpu0 at mainbus0: ARM926EJ-S rev 0 (ARM9EJ-S core)
> > mvsoc0 at mainbus0: Marvell MV88F5182 Rev. A2  Orion1
> > 
> > I've seen some indication in Linux that this is may be a early Marvell
> > Feroceon that merely claims to be ARM926.
> 
> cpu0 at mainbus0: Sheeva 88SV131 rev 1 (ARM9E-S core)
> mvsoc0 at mainbus0: Marvell 88F6281 Rev. A0  Kirkwood
> 
> the pthreads run fine on that.
> 
> Here's a small test program to run:
> 
> #include <sys/ucontext.h>
> 
> int
> main(void)
> {
>         printf("private=%#x\n", _lwp_getprivate());
>         _lwp_setprivate(0xdeadbeef);
>         printf("private=%#x\n", _lwp_getprivate());
>         printf("private=%#x\n", __lwp_getprivate_fast());
>         
>         return 0;
> }
> 

# ./lwptest                                                              
private=0x2002f000
private=0xdeadbeef
private=0

So, there's that.

        Jonathan Kollasch