ARM L2 cache support?

[KIYOHARA Takashi <kiyohara%kk.iij4u.or.jp@localhost>]

Hi! All,


What status to support for ARM L2 cache?
CPU core new of recent has L2 cache.  For instance, it is Cortex and
Marvell Sheeva.
My neither Sheevaplug nor Overo seem to work if L2 is not disabled now.

Do you know the person who is doing the activity of the L2 cache support?

Thanks,
--
kiyohara