Ken wrote:
Are you _sure_? You're talking about U19, right?
Ahhh. You're absolutely right. Mea culpa. The CPLD *is* used for the chip select lines for the ADCs and EEPROM. But contrary to what I wrote, the SPI bus is wired directly to the (U26)EEPROM. Looks like it's mostly for using the NAND flash on the TS-7250. The TS-7200 is based on NOR flash and doesn't have the SPI EEPROM.
So the TS-7200 on-chip ADCs look uncalibrated to me too. This is no problem if you have voltage references within your (hardware) application so that the ADC offset and gain can be calibrated. Uncalibrated, just using the approximation in the TS example code (i.e. commenting out the eeprom-accesses), it still works. I see modest offset errors but the gain is fairly close.
-Craig