Cache aliasing on >32k VIPT caches

[Imre Deak <imre.deak%teleca.com@localhost>]

Hi all,

according to the ARMv6 TRM:

1. If multiple Virtual Addresses are mapped onto the same physical address then 
for
   all mappings, bits [13:12] of the Virtual Addresses must be equal and the 
same as
   bits [13:12] of the physical address. Imposing this requirement on the 
virtual
   addresses is sometimes called page coloring.
   The same physical address can be mapped by TLB entries of different page 
sizes,
   including page sizes over 4KB.
2. Alternatively, if all mappings to a physical address are of a page size 
equal to
   4KB, then the restriction that bits[13:12] of the Virtual Address must equal
   bits[13:12] of the physical address is not necessary. Bits[13:12] of all 
Virtual
   Address aliases must still be equal.



So based on the above at the least we should adhere to 2., I'm guessing that
right now there isn't any case where we need 1. The current pmap code only 
considers
bit 12 to distinguish between colors, does this need to be corrected? As far as 
I
understand only bit 12 is significant for picking the cache index and thus 
color,
which would make the current code correct, but then again the TRM might just 
know
better..


diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c
index 2dd022d..9def301 100644
--- a/sys/arch/arm/arm/cpufunc.c
+++ b/sys/arch/arm/arm/cpufunc.c
@@ -1083,11 +1083,14 @@ get_cachetype_cp15()
                        arm_picache_ways = multiplier <<
                            (CPU_CT_xSIZE_ASSOC(isize) - 1);
 #if (ARM_MMU_V6) > 0
-                       if (CPU_CT_xSIZE_P & isize)
-                               arm_cache_prefer_mask |=
+                       if (CPU_CT_xSIZE_P & isize) {
+                               uint32_t mask =
                                    __BIT(9 + CPU_CT_xSIZE_SIZE(isize)
                                          - CPU_CT_xSIZE_ASSOC(isize))
                                    - PAGE_SIZE;
+                               mask |= mask << 1;
+                               arm_cache_prefer_mask |= mask;
+                       }
 #endif
                }
                arm_picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8);
@@ -1105,10 +1108,13 @@ get_cachetype_cp15()
                arm_pdcache_ways = multiplier <<
                    (CPU_CT_xSIZE_ASSOC(dsize) - 1);
 #if (ARM_MMU_V6) > 0
-               if (CPU_CT_xSIZE_P & dsize)
-                       arm_cache_prefer_mask |=
-                           __BIT(9 + CPU_CT_xSIZE_SIZE(dsize)
+               if (CPU_CT_xSIZE_P & dsize) {
+                       uint32_t mask = __BIT(9 + CPU_CT_xSIZE_SIZE(dsize)
                                  - CPU_CT_xSIZE_ASSOC(dsize)) - PAGE_SIZE;
+                       mask |= mask << 1;
+
+                       arm_cache_prefer_mask |= mask;
+               }
 #endif
        }
        arm_pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8);

--Imre