Re: i2c devices on TSC

[Julian Coleman <jdc%coris.org.uk@localhost>]

Hi,

> Yup.  Do you have a dmesg from a DS20L with these devices enabled?

Relevant parts below (full dmesg + envstat ouput at:

  https://www.coris.org.uk/jdc/Notes/20140221.html

).  I also started adding limits to the lmenv driver (need to finish that).

From previous notes:

  https://www.coris.org.uk/jdc/Notes/20131014.html

there are also chips at 0x23, 0x38 and 0x4e on iic0, but I'm not sure what
they are (0x23 is probably a PCF8574) nor what they control.  I'll try to
find time to have another go at finding more information about them.  For
other machines, it would be good to be certain what is at an address, so
it might need a bit of trial and error.

Regards,

Julian

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  alipm0 at pci0 dev 17 function 0: 74KHz clock
  iic0 at alipm0: I2C bus
  seeprom0 at iic0 addr 0x51: AT24Cxx or compatible EEPROM: size 256
  lmenv0 at iic0 addr 0x2c: ADM9240 rev 2
  lmenv1 at iic0 addr 0x2d: ADM9240 rev 2
  lmenv2 at iic0 addr 0x2e: ADM9240 rev 2
  lmenv3 at iic0 addr 0x2f: ADM9240 rev 2

  tsciic0 at tsc0
  iic1 at tsciic0: I2C bus
  spdmem0 at iic1 addr 0x50
  spdmem0: SDRAM (registered), data ECC, 256MB, 125MHz (PC-100)
  spdmem0: 12 rows, 10 cols, 2 banks, 4 banks/chip, 8.0ns cycle time
  spdmem0: tAA-tRCD-tRP-tRAS: 3-20-20-50
  spdmem0: voltage LvTTL (not 5V tolerant), refresh time 15.625us (self-refreshing)
  spdmem1 at iic1 addr 0x51
  spdmem1: SDRAM (registered), data ECC, 256MB, 125MHz (PC-100)
  spdmem1: 12 rows, 10 cols, 2 banks, 4 banks/chip, 8.0ns cycle time
  spdmem1: tAA-tRCD-tRP-tRAS: 3-20-20-50
  spdmem1: voltage LvTTL (not 5V tolerant), refresh time 15.625us (self-refreshing)
  spdmem2 at iic1 addr 0x52
  spdmem2: SDRAM (registered), data ECC, 256MB, 125MHz (PC-100)
  spdmem2: 12 rows, 10 cols, 2 banks, 4 banks/chip, 8.0ns cycle time
  spdmem2: tAA-tRCD-tRP-tRAS: 3-20-20-50
  spdmem2: voltage LvTTL (not 5V tolerant), refresh time 15.625us (self-refreshing)
  spdmem3 at iic1 addr 0x53
  spdmem3: SDRAM (registered), data ECC, 256MB, 125MHz (PC-100)
  spdmem3: 12 rows, 10 cols, 2 banks, 4 banks/chip, 8.0ns cycle time
  spdmem3: tAA-tRCD-tRP-tRAS: 3-20-20-50
  spdmem3: voltage LvTTL (not 5V tolerant), refresh time 15.625us (self-refreshing)
  spdmem4 at iic1 addr 0x54
  spdmem4: SDRAM (registered), data ECC, 256MB, 125MHz (PC-100)
  spdmem4: 12 rows, 11 cols, 1 banks, 4 banks/chip, 8.0ns cycle time
  spdmem4: tAA-tRCD-tRP-tRAS: 3-20-20-50
  spdmem4: voltage LvTTL (not 5V tolerant), refresh time 15.625us (self-refreshing)
  spdmem5 at iic1 addr 0x55
  spdmem5: SDRAM (registered), data ECC, 256MB, 125MHz (PC-100)
  spdmem5: 12 rows, 11 cols, 1 banks, 4 banks/chip, 8.0ns cycle time
  spdmem5: tAA-tRCD-tRP-tRAS: 3-20-20-50
  spdmem5: voltage LvTTL (not 5V tolerant), refresh time 15.625us (self-refreshing)
  spdmem6 at iic1 addr 0x56
  spdmem6: SDRAM (registered), data ECC, 256MB, 125MHz (PC-100)
  spdmem6: 12 rows, 11 cols, 1 banks, 4 banks/chip, 8.0ns cycle time
  spdmem6: tAA-tRCD-tRP-tRAS: 3-20-20-50
  spdmem6: voltage LvTTL (not 5V tolerant), refresh time 15.625us (self-refreshing)
  spdmem7 at iic1 addr 0x57
  spdmem7: SDRAM (registered), data ECC, 256MB, 125MHz (PC-100)
  spdmem7: 12 rows, 11 cols, 1 banks, 4 banks/chip, 8.0ns cycle time
  spdmem7: tAA-tRCD-tRP-tRAS: 3-20-20-50
  spdmem7: voltage LvTTL (not 5V tolerant), refresh time 15.625us (self-refreshing)
  lmenv4 at iic1 addr 0x2e: ADM9240 rev 2
  lmenv5 at iic1 addr 0x2f: ADM9240 rev 2

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