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[pkgsrc/trunk]: pkgsrc/cad/iverilog Import iverilog (Icarus Verilog) 10.1.1 a...
details: https://anonhg.NetBSD.org/pkgsrc/rev/d47475d60d73
branches: trunk
changeset: 353536:d47475d60d73
user: kamil <kamil%pkgsrc.org@localhost>
date: Sat Oct 08 23:01:45 2016 +0000
description:
Import iverilog (Icarus Verilog) 10.1.1 as cad/iverilog
It's a rename of cad/verilog to a better name.
Updated DESCR for new package:
Icarus Verilog is intended to compile ALL of the Verilog HDL as described in
the IEEE-1364 standard. Of course, it's not quite there yet. It does currently
handle a mix of structural and behavioral constructs.
Icarus Verilog is not aimed at being a simulator in the traditional sense, but
a compiler that generates code employed by back-end tools.
No objections to rename from <gdt>
diffstat:
cad/iverilog/DESCR | 6 +++
cad/iverilog/Makefile | 37 +++++++++++++++++++
cad/iverilog/PLIST | 58 ++++++++++++++++++++++++++++++
cad/iverilog/buildlink3.mk | 16 ++++++++
cad/iverilog/distinfo | 9 ++++
cad/iverilog/patches/patch-aa | 14 +++++++
cad/iverilog/patches/patch-ad | 25 ++++++++++++
cad/iverilog/patches/patch-cadpli_Makefile | 17 ++++++++
8 files changed, 182 insertions(+), 0 deletions(-)
diffs (214 lines):
diff -r 4e9ad59ef102 -r d47475d60d73 cad/iverilog/DESCR
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cad/iverilog/DESCR Sat Oct 08 23:01:45 2016 +0000
@@ -0,0 +1,6 @@
+Icarus Verilog is intended to compile ALL of the Verilog HDL as described in
+the IEEE-1364 standard. Of course, it's not quite there yet. It does currently
+handle a mix of structural and behavioral constructs.
+
+Icarus Verilog is not aimed at being a simulator in the traditional sense, but
+a compiler that generates code employed by back-end tools.
diff -r 4e9ad59ef102 -r d47475d60d73 cad/iverilog/Makefile
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cad/iverilog/Makefile Sat Oct 08 23:01:45 2016 +0000
@@ -0,0 +1,37 @@
+# $NetBSD: Makefile,v 1.1 2016/10/08 23:01:45 kamil Exp $
+#
+
+DISTNAME= verilog-10.1.1
+# There is confision in naming of this software, use iverilog as it's saner
+PKGNAME= i${DISTNAME}
+CATEGORIES= cad
+MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v10/
+# FTP has newer release than GitHub tag
+#MASTER_SITES= ${MASTER_SITE_GITHUB:=steveicarus/}
+#GITHUB_TAG= v${PKGVERSION_NOREV:S/./_/}
+
+MAINTAINER= dmcmahill%NetBSD.org@localhost
+HOMEPAGE= http://iverilog.icarus.com/
+COMMENT= Verilog simulation and synthesis tool (stable release version)
+LICENSE= gnu-gpl-v2
+
+USE_LANGUAGES= c c++
+
+GNU_CONFIGURE= yes
+USE_TOOLS+= gmake bison lex
+TEST_TARGET= check
+
+INSTALLATION_DIRS+= share/doc/ivl
+
+# Additional files
+post-install:
+ cd ${WRKSRC}; ${INSTALL_DATA} \
+ QUICK_START.txt \
+ README.txt \
+ ${DESTDIR}${PREFIX}/share/doc/ivl
+
+.include "../../devel/gperf/buildlink3.mk"
+.include "../../devel/zlib/buildlink3.mk"
+.include "../../archivers/bzip2/buildlink3.mk"
+.include "../../mk/readline.buildlink3.mk"
+.include "../../mk/bsd.pkg.mk"
diff -r 4e9ad59ef102 -r d47475d60d73 cad/iverilog/PLIST
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cad/iverilog/PLIST Sat Oct 08 23:01:45 2016 +0000
@@ -0,0 +1,58 @@
+@comment $NetBSD: PLIST,v 1.1 2016/10/08 23:01:45 kamil Exp $
+bin/iverilog
+bin/iverilog-vpi
+bin/vvp
+include/iverilog/_pli_types.h
+include/iverilog/acc_user.h
+include/iverilog/ivl_target.h
+include/iverilog/sv_vpi_user.h
+include/iverilog/veriuser.h
+include/iverilog/vpi_user.h
+lib/ivl/blif-s.conf
+lib/ivl/blif.conf
+lib/ivl/blif.tgt
+lib/ivl/cadpli.vpl
+lib/ivl/include/constants.vams
+lib/ivl/include/disciplines.vams
+lib/ivl/ivl
+lib/ivl/ivlpp
+lib/ivl/null-s.conf
+lib/ivl/null.conf
+lib/ivl/null.tgt
+lib/ivl/pcb-s.conf
+lib/ivl/pcb.conf
+lib/ivl/pcb.tgt
+lib/ivl/sizer-s.conf
+lib/ivl/sizer.conf
+lib/ivl/sizer.tgt
+lib/ivl/stub-s.conf
+lib/ivl/stub.conf
+lib/ivl/stub.tgt
+lib/ivl/system.sft
+lib/ivl/system.vpi
+lib/ivl/v2005_math.sft
+lib/ivl/v2005_math.vpi
+lib/ivl/v2009.sft
+lib/ivl/v2009.vpi
+lib/ivl/va_math.sft
+lib/ivl/va_math.vpi
+lib/ivl/vhdl-s.conf
+lib/ivl/vhdl.conf
+lib/ivl/vhdl.tgt
+lib/ivl/vhdl_sys.sft
+lib/ivl/vhdl_sys.vpi
+lib/ivl/vhdlpp
+lib/ivl/vlog95-s.conf
+lib/ivl/vlog95.conf
+lib/ivl/vlog95.tgt
+lib/ivl/vpi_debug.vpi
+lib/ivl/vvp-s.conf
+lib/ivl/vvp.conf
+lib/ivl/vvp.tgt
+lib/libveriuser.a
+lib/libvpi.a
+man/man1/iverilog-vpi.1
+man/man1/iverilog.1
+man/man1/vvp.1
+share/doc/ivl/QUICK_START.txt
+share/doc/ivl/README.txt
diff -r 4e9ad59ef102 -r d47475d60d73 cad/iverilog/buildlink3.mk
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cad/iverilog/buildlink3.mk Sat Oct 08 23:01:45 2016 +0000
@@ -0,0 +1,16 @@
+# $NetBSD: buildlink3.mk,v 1.1 2016/10/08 23:01:45 kamil Exp $
+
+BUILDLINK_TREE+= iverilog
+
+.if !defined(IVERILOG_BUILDLINK3_MK)
+IVERILOG_BUILDLINK3_MK:=
+
+BUILDLINK_API_DEPENDS.iverilog+= iverilog>=10.1.1
+BUILDLINK_PKGSRCDIR.iverilog?= ../../cad/iverilog
+
+.include "../../devel/gperf/buildlink3.mk"
+.include "../../devel/zlib/buildlink3.mk"
+.include "../../archivers/bzip2/buildlink3.mk"
+.endif # IVERILOG_BUILDLINK3_MK
+
+BUILDLINK_TREE+= -iverilog
diff -r 4e9ad59ef102 -r d47475d60d73 cad/iverilog/distinfo
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cad/iverilog/distinfo Sat Oct 08 23:01:45 2016 +0000
@@ -0,0 +1,9 @@
+$NetBSD: distinfo,v 1.1 2016/10/08 23:01:45 kamil Exp $
+
+SHA1 (verilog-10.1.1.tar.gz) = 7f4cead8cabb90cc4525951357c43866ca710749
+RMD160 (verilog-10.1.1.tar.gz) = 77c933b712ab027b13a81e3eead7ee4f565741b7
+SHA512 (verilog-10.1.1.tar.gz) = a57fdce3d870be8ce39eb3050dabd5a2d4d491c657b85ccbf775bef7fa9a6889a18bf4d2508341ef2cc17d872b5d6c802d4fd8585e4ec7952526699ebb24bfac
+Size (verilog-10.1.1.tar.gz) = 1684925 bytes
+SHA1 (patch-aa) = cf075110416f6db0892129796cd83b8ae8de55fa
+SHA1 (patch-ad) = bf7d227ed3b321021d8aff54cd008f4b2a1557b9
+SHA1 (patch-cadpli_Makefile) = ed21a5f529ac449c26b831cbd5fde052d9ed5466
diff -r 4e9ad59ef102 -r d47475d60d73 cad/iverilog/patches/patch-aa
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cad/iverilog/patches/patch-aa Sat Oct 08 23:01:45 2016 +0000
@@ -0,0 +1,14 @@
+$NetBSD: patch-aa,v 1.1 2016/10/08 23:01:45 kamil Exp $
+
+gcc44 fixes
+
+--- elab_net.cc.orig 2010-09-27 17:42:32.000000000 +0000
++++ elab_net.cc
+@@ -26,6 +26,7 @@
+
+ # include <cstdlib>
+ # include <cstring>
++# include <memory>
+ # include <iostream>
+ # include "ivl_assert.h"
+
diff -r 4e9ad59ef102 -r d47475d60d73 cad/iverilog/patches/patch-ad
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cad/iverilog/patches/patch-ad Sat Oct 08 23:01:45 2016 +0000
@@ -0,0 +1,25 @@
+$NetBSD: patch-ad,v 1.1 2016/10/08 23:01:45 kamil Exp $
+
+make sure no one sneaks a -O* in on us via one of these variables
+set in the environment
+
+--- Makefile.in.orig 2013-08-20 04:10:31.000000000 +0900
++++ Makefile.in 2013-12-20 11:35:09.000000000 +0900
+@@ -222,6 +222,17 @@
+
+ lexor.o: lexor.cc parse.h
+
++# make sure no one sneaks a -O* in on us via one of these variables
++# set in the environment
++CXX_NOOPT=$(CXX:-O%=)
++CPPFLAGS_NOOPT=$(CPPFLAGS:-O%=)
++CXXFLAGS_NOOPT=$(CXXFLAGS:-O%=)
++
++parse.o: parse.cc
++ @[ -d dep ] || mkdir dep
++ $(CXX_NOOPT) $(CPPFLAGS_NOOPT) $(CXXFLAGS_NOOPT) -MD -c $< -o $*.o
++ mv $*.d dep/$*.d
++
+ parse.o: parse.cc
+
+ # Build this in two steps to avoid parallel build issues (see pr3462585)
diff -r 4e9ad59ef102 -r d47475d60d73 cad/iverilog/patches/patch-cadpli_Makefile
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/cad/iverilog/patches/patch-cadpli_Makefile Sat Oct 08 23:01:45 2016 +0000
@@ -0,0 +1,17 @@
+$NetBSD: patch-cadpli_Makefile,v 1.1 2016/10/08 23:01:45 kamil Exp $
+
+gcc -std=gnu99 -shared -L/usr/lib -Wl,-R/usr/lib -L/usr/pkg/lib -Wl,-R/usr/pkg/lib -o cadpli.vpl cadpli.o ../libveriuser/libveriuser.o -L../vvp -lvpi
+mkdir: dep: Not a directory
+Makefile:52: recipe for target 'dep' failed
+
+--- cadpli/Makefile.in~ 2013-08-20 04:10:31.000000000 +0900
++++ cadpli/Makefile.in 2013-12-20 22:03:29.000000000 +0900
+@@ -51,7 +51,7 @@ check: all
+ dep:
+ mkdir dep
+
+-%.o: %.c
++%.o: %.c dep
+ $(CC) $(CPPFLAGS) $(CFLAGS) @DEPENDENCY_FLAG@ -c $<
+ mv $*.d dep
+
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