port-arm/59654: arm bus_dma is missing PREREAD memory barrier and others can be relaxed.

[nick.hudson%gmx.co.uk@localhost]

>Number:         59654
>Category:       port-arm
>Synopsis:       arm bus_dma is missing PREREAD memory barrier and others can be relaxed.
>Confidential:   no
>Severity:       serious
>Priority:       medium
>Responsible:    port-arm-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Sun Sep 14 09:50:00 +0000 2025
>Originator:     Nick Hudson
>Release:        NetBSD 11.99.2
>Organization:
	sofasoft ltd.
>Environment:
Architecture: arm (aarch32+aarch64)
>Description:
	The risc-v bus_dma backend code (taken from the arm equivalent) is
	missing a PREREAD barrier. A typical sequence is

	1. loads and stores before DMA buffer may be allocated for the purpose
	2. bus_dmamap_sync(BUS_DMASYNC_PREREAD)
	3. store to register or DMA descriptor to trigger DMA

	and requires a load/store-before-load barrier.

	PREWRITE and POSTREAD barriers are

		cpu_drain_writebuf // aka dsb(sy) for aarch64

	which can be relaxed.
>How-To-Repeat:
	n/a	
>Fix:
	in progress.