port-riscv/59653: risc-v bus_dma is missing PREREAD memory barrier and others can be relaxed.

[nick.hudson%gmx.co.uk@localhost]

>Number:         59653
>Category:       port-riscv
>Synopsis:       risc-v bus_dma is missing PREREAD memory barrier and others can be relaxed.
>Confidential:   no
>Severity:       serious
>Priority:       medium
>Responsible:    port-riscv-maintainer
>State:          open
>Class:          sw-bug
>Submitter-Id:   net
>Arrival-Date:   Sun Sep 14 09:25:00 +0000 2025
>Originator:     Nick Hudson
>Release:        NetBSD 11.99.2
>Organization:
	sofasoft ltd.
>Environment:
Architecture: riscv64
Machine: riscv64
>Description:
	The risc-v bus_dma backend code (taken from the arm equivalent) is
	missing a PREREAD barrier. A typical sequence is
         
	1. loads and stores before DMA buffer may be allocated for the purpose
	2. bus_dmamap_sync(BUS_DMASYNC_PREREAD)
	3. store to register or DMA descriptor to trigger DMA
	
	and requires a load/store-before-load barrier at (2).
	
	PREWRITE and POSTREAD barriers are
	
		fence iorw,iorw
		
	which can be relaxed.
>How-To-Repeat:
	
>Fix: