Re: kern/44395: Request a bit patch for ale(4) driver.

[Masanori Kanaoka <kanaoka%ann.hi-ho.ne.jp@localhost>]

The following reply was made to PR kern/44395; it has been noted by GNATS.

From: Masanori Kanaoka <kanaoka%ann.hi-ho.ne.jp@localhost>
To: gnats-bugs%NetBSD.org@localhost, gnats-admin%netbsd.org@localhost
Cc: 
Subject: Re: kern/44395: Request a bit patch for ale(4) driver.
Date: Thu, 20 Jan 2011 00:23:17 +0900 (JST)

 Hi
 
 I update a patch for ale(4) and atphy(4).
 Would you please apply it.
 
 ---
  Masanori Kanaoka        kanaoka AT ann.hi-ho.ne.jp
 
 
 Index: sys/dev/mii/atphy.c
 ===================================================================
 RCS file: /ftp/cvs/src/sys/dev/mii/atphy.c,v
 retrieving revision 1.7
 diff -u -r1.7 atphy.c
 --- sys/dev/mii/atphy.c        11 Dec 2010 18:10:16 -0000      1.7
 +++ sys/dev/mii/atphy.c        19 Jan 2011 14:58:21 -0000
 @@ -118,6 +118,7 @@
        struct mii_attach_args *ma = aux;
        struct mii_data *mii = ma->mii_data;
        const struct mii_phydesc *mpd;
 +      uint16_t bmsr;
  
        mpd = mii_phy_match(ma, etphys);
        aprint_naive(": Media interface\n");
 @@ -135,7 +136,8 @@
  
        PHY_RESET(sc);
  
 -      sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
 +      bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
 +      sc->mii_capabilities = bmsr & ma->mii_capmask;
        if (sc->mii_capabilities & BMSR_EXTSTAT)
                sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
  
 @@ -220,8 +222,7 @@
                /*
                 * Reset the PHY so all changes take effect.
                 */
 -              PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |
 -                  BMCR_STARTNEG);
 +              PHY_WRITE(sc, MII_BMCR, bmcr |  BMCR_AUTOEN | BMCR_STARTNEG);
  done:
                break;
  
 @@ -364,9 +365,13 @@
        reg |= ATPHY_SCR_POLARITY_REVERSAL;
        PHY_WRITE(sc, ATPHY_SCR, reg);
  
 -      /* Workaround F1 bug to reset phy. */
        atphy_mii_phy_auto(sc);
  
 +      /* Workaround F1 bug to reset phy. */
 +      reg = PHY_READ(sc, MII_BMCR);
 +      reg |= BMCR_RESET;
 +      PHY_WRITE(sc, MII_BMCR, reg);
 +
        for (i = 0; i < 1000; i++) {
                DELAY(1);
                if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
 @@ -386,7 +391,7 @@
        if (sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX))
                PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
                    GTCR_ADV_1000THDX);
 -      PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
 +      PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
  
        return EJUSTRETURN;
  }
 Index: sys/dev/pci/if_ale.c
 ===================================================================
 RCS file: /ftp/cvs/src/sys/dev/pci/if_ale.c,v
 retrieving revision 1.12
 diff -u -r1.12 if_ale.c
 --- sys/dev/pci/if_ale.c       20 Jul 2010 09:17:24 -0000      1.12
 +++ sys/dev/pci/if_ale.c       19 Jan 2011 15:00:13 -0000
 @@ -367,12 +367,12 @@
        ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr,
            ATPHY_DBG_ADDR, 0x04);
        ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr,
 -          ATPHY_DBG_ADDR, 0x8BBB);
 +          ATPHY_DBG_DATA, 0x8BBB);
        /* 10BT center tap voltage. */
        ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr,
            ATPHY_DBG_ADDR, 0x05);
        ale_miibus_writereg(sc->sc_dev, sc->ale_phyaddr,
 -          ATPHY_DBG_ADDR, 0x2C46);
 +          ATPHY_DBG_DATA, 0x2C46);
  
  #undef        ATPHY_DBG_ADDR
  #undef        ATPHY_DBG_DATA
 @@ -1910,7 +1910,7 @@
  
        reg = CSR_READ_4(sc, ALE_MAC_CFG);
        if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
 -              reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
 +              reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
                CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
        }
  
 @@ -2015,7 +2015,7 @@
  
                ETHER_FIRST_MULTI(step, ec, enm);
                while (enm != NULL) {
 -                      crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
 +                      crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
                        mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
                        ETHER_NEXT_MULTI(step, enm);
                }