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Re: port-i386/39950: Missing features 2-4 support in /proc/cpuinfo for AMD CPUs on i386
The following reply was made to PR port-i386/39950; it has been noted by GNATS.
From: Nicolas Joly <njoly%pasteur.fr@localhost>
To: gnats-bugs%NetBSD.org@localhost
Cc:
Subject: Re: port-i386/39950: Missing features 2-4 support in /proc/cpuinfo for
AMD CPUs on i386
Date: Wed, 14 Jul 2010 18:57:58 +0200
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On Tue, Nov 18, 2008 at 12:45:00PM +0000, Bernd Ernesti wrote:
> >Number: 39950
> >Category: port-i386
> >Synopsis: Missing features 2-4 support in /proc/cpuinfo for AMD CPUs
> >on i386
> >Confidential: no
> >Severity: non-critical
> >Priority: medium
> >Responsible: port-i386-maintainer
> >State: open
> >Class: sw-bug
> >Submitter-Id: net
> >Arrival-Date: Tue Nov 18 12:45:00 +0000 2008
> >Originator: Bernd Ernesti
> >Release: NetBSD 5.99.02
> >Organization:
> >Environment:
> System: NetBSD 5.99.02
> Architecture: i386
> Machine: i386
> >Description:
> /proc/cpuinfo is incomplete because it doesn't show all cpu flags.
Can you try the attached patch ?
--
Nicolas Joly
Biological Software and Databanks.
Institut Pasteur, Paris.
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Index: sys/arch/x86/x86/procfs_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/x86/x86/procfs_machdep.c,v
retrieving revision 1.1
diff -u -p -r1.1 procfs_machdep.c
--- sys/arch/x86/x86/procfs_machdep.c 8 Jul 2010 11:25:00 -0000 1.1
+++ sys/arch/x86/x86/procfs_machdep.c 14 Jul 2010 16:53:26 -0000
@@ -53,6 +53,8 @@ __KERNEL_RCSID(0, "$NetBSD: procfs_machd
#include <miscfs/procfs/procfs.h>
#include <machine/cpu.h>
+#include <machine/cputypes.h>
+#include <machine/cpuvar.h>
#include <machine/reg.h>
#include <machine/specialreg.h>
@@ -64,13 +66,13 @@ static const char * const x86_features[]
"fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
"cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
"pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
- "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
-#ifdef __x86_64__
+ "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
+
/* AMD-defined */
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
- NULL, "fxsr_opt", "rdtscp", NULL, NULL, "lm", "3dnowext", "3dnow",
+ NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL,
+ NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm", "3dnowext", "3dnow",
/* Transmeta-defined */
"recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
@@ -79,31 +81,30 @@ static const char * const x86_features[]
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/* Linux-defined */
- "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
- "constant_tsc", NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr", NULL, NULL, NULL, NULL,
+ "constant_tsc", "up", NULL, "arch_perfmon", "pebs", "bts", NULL, NULL,
+ "rep_good", NULL, NULL, NULL, "nopl", "amdc1e", "xtopology", NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/* Intel-defined */
- "pni", NULL, NULL, "monitor", "ds_cpi", "vmx", NULL, "est",
- "tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ "pni", "pclmulqdq", "dtes64", "monitor", "ds_cpl", "vmx", "smx", "est",
+ "tm2", "ssse3", "cid", NULL, "fma", "cx16", "xtpr", "pdcm",
+ NULL, NULL, "dca", "sse4_1", "sse4_2", "x2apic", NULL, "popcnt",
+ NULL, "aes", "xsave", NULL, "avx", NULL, NULL, NULL,
/* VIA/Cyrix/Centaur-defined */
NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/* AMD defined */
- "lahf_lm", "cmp_legacy", "svm", NULL, "cr8_legacy", NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ "lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy", "abm",
"sse4a", "misalignsse",
+ "3dnowprefetch", "osvw", "ibs", "sse5", "skinit", "wdt", NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
-#endif
+ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
};
+CTASSERT(__arraycount(x86_features) % 32 == 0);
static int procfs_getonecpu(int, struct cpu_info *, char *, int *);
@@ -147,12 +148,26 @@ static int
procfs_getonecpu(int xcpu, struct cpu_info *ci, char *bf, int *len)
{
int left, l, i;
- char featurebuf[256], *p;
+ char featurebuf[512], *p;
+ uint32_t features[__arraycount(x86_features) / 32];
+
+ memset(features, 0, sizeof(features));
+ features[0] = ci->ci_feat_val[0];
+ switch (cpu_vendor) {
+ case CPUVENDOR_AMD:
+ case CPUVENDOR_INTEL:
+ features[1] = ci->ci_feat_val[2];
+ features[4] = ci->ci_feat_val[1];
+ features[6] = ci->ci_feat_val[3];
+ break;
+ default:
+ break;
+ }
p = featurebuf;
left = sizeof(featurebuf);
- for (i = 0; i < 32; i++) {
- if ((ci->ci_feat_val[0] & (1 << i)) && x86_features[i]) {
+ for (i = 0; i < __arraycount(x86_features); i++) {
+ if ((features[i / 32] & (1 << (i % 32))) && x86_features[i]) {
l = snprintf(p, left, "%s ", x86_features[i]);
left -= l;
p += l;
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