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Re: port-arm/43339: IPL_NONE == IPL_SOFTNET on arm ports and itcauses assertion panic
The following reply was made to PR port-arm/43339; it has been noted by GNATS.
From: Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>
To: gnats-bugs%NetBSD.org@localhost
Cc: rmind%NetBSD.org@localhost, port-arm-maintainer%NetBSD.org@localhost,
gnats-admin%NetBSD.org@localhost,
netbsd-bugs%NetBSD.org@localhost, tsutsui%ceres.dti.ne.jp@localhost
Subject: Re: port-arm/43339: IPL_NONE == IPL_SOFTNET on arm ports and itcauses
assertion panic
Date: Wed, 2 Jun 2010 23:58:21 +0900
> > >Fix:
> > Set proper IPL_SOFTfoo values?
:
> Right, while from mutex(9) perspective IPL_NONE and IPL_SOFT* behave same,
> part of the reason for these definitions is a use for various assertions.
> Therefore, definitions should have unique values.
Here is a dumb mechanical patch (tested only on shark):
---
Index: acorn32/include/intr.h
===================================================================
RCS file: /cvsroot/src/sys/arch/acorn32/include/intr.h,v
retrieving revision 1.8
diff -u -r1.8 intr.h
--- acorn32/include/intr.h 27 Apr 2008 18:58:43 -0000 1.8
+++ acorn32/include/intr.h 2 Jun 2010 14:49:46 -0000
@@ -41,7 +41,6 @@
/* Hardware Interrupt Priority Levels are not mutually exclusive. */
#define IPL_NONE 0
-#ifdef __HAVE_FAST_SOFTINTS
#define IPL_SOFTCLOCK 1
#define IPL_SOFTBIO 2
#define IPL_SOFTNET 3
@@ -50,16 +49,6 @@
#define IPL_SCHED 6
#define IPL_HIGH 7
#define NIPL 8
-#else
-#define IPL_VM 1
-#define IPL_SCHED 2
-#define IPL_HIGH 3
-#define IPL_SOFTSERIAL IPL_NONE
-#define IPL_SOFTNET IPL_NONE
-#define IPL_SOFTBIO IPL_NONE
-#define IPL_SOFTCLOCK IPL_NONE
-#define NIPL 4
-#endif
#define IST_UNUSABLE -1 /* interrupt cannot be used */
#define IST_NONE 0 /* none (dummy) */
Index: arm/arm32/intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/arm32/intr.c,v
retrieving revision 1.30
diff -u -r1.30 intr.c
--- arm/arm32/intr.c 19 Nov 2008 06:30:49 -0000 1.30
+++ arm/arm32/intr.c 2 Jun 2010 14:49:47 -0000
@@ -65,10 +65,14 @@
spl_masks[loop] = 0xffffffff;
}
- spl_masks[IPL_VM] = irqmasks[IPL_VM];
- spl_masks[IPL_SCHED] = irqmasks[IPL_SCHED];
- spl_masks[IPL_HIGH] = irqmasks[IPL_HIGH];
- spl_masks[IPL_NONE] = irqmasks[IPL_NONE];
+ spl_masks[IPL_VM] = irqmasks[IPL_VM];
+ spl_masks[IPL_SCHED] = irqmasks[IPL_SCHED];
+ spl_masks[IPL_HIGH] = irqmasks[IPL_HIGH];
+ spl_masks[IPL_SOFTSERIAL] = irqmasks[IPL_SOFTSERIAL];
+ spl_masks[IPL_SOFTNET] = irqmasks[IPL_SOFTNET];
+ spl_masks[IPL_SOFTBIO] = irqmasks[IPL_SOFTBIO];
+ spl_masks[IPL_SOFTCLOCK] = irqmasks[IPL_SOFTCLOCK];
+ spl_masks[IPL_NONE] = irqmasks[IPL_NONE];
}
Index: arm/at91/at91aic.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/at91/at91aic.c,v
retrieving revision 1.3
diff -u -r1.3 at91aic.c
--- arm/at91/at91aic.c 23 Oct 2009 06:53:12 -0000 1.3
+++ arm/at91/at91aic.c 2 Jun 2010 14:49:47 -0000
@@ -145,23 +145,20 @@
aic_imask[ipl] = aic_irqs;
}
- aic_imask[IPL_NONE] = 0;
+ /* IPL_NONE must open up all interrupts */
+ KASSERT(aic_imask[IPL_NONE] == 0);
+ KASSERT(aic_imask[IPL_SOFTCLOCK] == 0);
+ KASSERT(aic_imask[IPL_SOFTBIO] == 0);
+ KASSERT(aic_imask[IPL_SOFTNET] == 0);
+ KASSERT(aic_imask[IPL_SOFTSERIAL] == 0);
/*
- * splvm() blocks all interrupts that use the kernel memory
- * allocation facilities.
+ * Enforce a hierarchy that gives "slow" device (or devices with
+ * limited input buffer space/"real-time" requirements) a better
+ * chance at not dropping data.
*/
- aic_imask[IPL_VM] |= aic_imask[IPL_NONE];
-
- /*
- * splclock() must block anything that uses the scheduler.
- */
- aic_imask[IPL_CLOCK] |= aic_imask[IPL_VM];
-
- /*
- * splhigh() must block "everything".
- */
- aic_imask[IPL_HIGH] |= aic_imask[IPL_CLOCK];
+ aic_imask[IPL_SCHED] |= aic_imask[IPL_VM];
+ aic_imask[IPL_HIGH] |= aic_imask[IPL_SCHED];
/*
* Now compute which IRQs must be blocked when servicing any
Index: arm/ep93xx/ep93xx_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/ep93xx/ep93xx_intr.c,v
retrieving revision 1.13
diff -u -r1.13 ep93xx_intr.c
--- arm/ep93xx/ep93xx_intr.c 28 Apr 2008 20:23:14 -0000 1.13
+++ arm/ep93xx/ep93xx_intr.c 2 Jun 2010 14:49:47 -0000
@@ -150,9 +150,17 @@
KASSERT(vic1_imask[IPL_NONE] == 0);
KASSERT(vic2_imask[IPL_NONE] == 0);
+ KASSERT(vic1_imask[IPL_SOFTCLOCK] == 0);
+ KASSERT(vic2_imask[IPL_SOFTCLOCK] == 0);
+ KASSERT(vic1_imask[IPL_SOFTBIO] == 0);
+ KASSERT(vic2_imask[IPL_SOFTBIO] == 0);
+ KASSERT(vic1_imask[IPL_SOFTNET] == 0);
+ KASSERT(vic2_imask[IPL_SOFTNET] == 0);
+ KASSERT(vic1_imask[IPL_SOFTSERIAL] == 0);
+ KASSERT(vic2_imask[IPL_SOFTSERIAL] == 0);
/*
- * splclock() must block anything that uses the scheduler.
+ * splsched() must block anything that uses the scheduler.
*/
vic1_imask[IPL_SCHED] |= vic1_imask[IPL_VM];
vic2_imask[IPL_SCHED] |= vic2_imask[IPL_VM];
Index: arm/footbridge/isa/isa_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/footbridge/isa/isa_machdep.c,v
retrieving revision 1.16
diff -u -r1.16 isa_machdep.c
--- arm/footbridge/isa/isa_machdep.c 20 Aug 2009 12:51:28 -0000 1.16
+++ arm/footbridge/isa/isa_machdep.c 2 Jun 2010 14:49:48 -0000
@@ -203,12 +203,6 @@
imask[level] = irqs;
}
- imask[IPL_NONE] = 0;
- imask[IPL_SOFTCLOCK] |= imask[IPL_NONE];
- imask[IPL_SOFTBIO] |= imask[IPL_SOFTCLOCK];
- imask[IPL_SOFTNET] |= imask[IPL_SOFTBIO];
- imask[IPL_SOFTSERIAL] |= imask[IPL_SOFTNET];
- imask[IPL_VM] |= imask[IPL_SOFTSERIAL];
imask[IPL_SCHED] |= imask[IPL_VM];
imask[IPL_HIGH] |= imask[IPL_SCHED];
Index: arm/ixp12x0/ixp12x0_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/ixp12x0/ixp12x0_intr.c,v
retrieving revision 1.19
diff -u -r1.19 ixp12x0_intr.c
--- arm/ixp12x0/ixp12x0_intr.c 28 Apr 2008 20:23:14 -0000 1.19
+++ arm/ixp12x0/ixp12x0_intr.c 2 Jun 2010 14:49:48 -0000
@@ -206,21 +206,29 @@
KASSERT(imask[IPL_NONE] == 0);
KASSERT(pci_imask[IPL_NONE] == 0);
+ KASSERT(imask[IPL_SOFTCLOCK] == 0);
+ KASSERT(pci_imask[IPL_SOFTCLOCK] == 0);
+ KASSERT(imask[IPL_SOFTBIO] == 0);
+ KASSERT(pci_imask[IPL_SOFTBIO] == 0);
+ KASSERT(imask[IPL_SOFTNET] == 0);
+ KASSERT(pci_imask[IPL_SOFTNET] == 0);
+ KASSERT(imask[IPL_SOFTSERIAL] == 0);
+ KASSERT(pci_imask[IPL_SOFTSERIAL] == 0);
KASSERT(imask[IPL_VM] != 0);
KASSERT(pci_imask[IPL_VM] != 0);
/*
- * splclock() must block anything that uses the scheduler.
+ * splsched() must block anything that uses the scheduler.
*/
- imask[IPL_CLOCK] |= imask[IPL_VM];
- pci_imask[IPL_CLOCK] |= pci_imask[IPL_VM];
+ imask[IPL_SCHED] |= imask[IPL_VM];
+ pci_imask[IPL_SCHED] |= pci_imask[IPL_VM];
/*
* splhigh() must block "everything".
*/
- imask[IPL_HIGH] |= imask[IPL_CLOCK];
- pci_imask[IPL_HIGH] |= pci_imask[IPL_CLOCK];
+ imask[IPL_HIGH] |= imask[IPL_SCHED];
+ pci_imask[IPL_HIGH] |= pci_imask[IPL_SCHED];
/*
* Now compute which IRQs must be blocked when servicing any
Index: arm/xscale/i80321_icu.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/i80321_icu.c,v
retrieving revision 1.19
diff -u -r1.19 i80321_icu.c
--- arm/xscale/i80321_icu.c 5 Jan 2009 06:03:39 -0000 1.19
+++ arm/xscale/i80321_icu.c 2 Jun 2010 14:49:48 -0000
@@ -187,7 +187,11 @@
i80321_imask[ipl] = irqs;
}
- i80321_imask[IPL_NONE] = 0;
+ KASSERT(i80321_imask[IPL_NONE] == 0);
+ KASSERT(i80321_imask[IPL_SOFTCLOCK] == 0);
+ KASSERT(i80321_imask[IPL_SOFTBIO] == 0);
+ KASSERT(i80321_imask[IPL_SOFTNET] == 0);
+ KASSERT(i80321_imask[IPL_SOFTSERIAL] == 0);
/*
* Enforce a hierarchy that gives "slow" device (or devices with
Index: arm/xscale/ixp425_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/ixp425_intr.c,v
retrieving revision 1.20
diff -u -r1.20 ixp425_intr.c
--- arm/xscale/ixp425_intr.c 21 Oct 2009 14:15:50 -0000 1.20
+++ arm/xscale/ixp425_intr.c 2 Jun 2010 14:49:48 -0000
@@ -226,6 +226,11 @@
ixp425_imask[IPL_SOFTBIO] = SI_TO_IRQBIT(SI_SOFTBIO);
ixp425_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
ixp425_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
+#else
+ KASSERT(ixp425_imask[IPL_SOFTCLOCK] == 0);
+ KASSERT(ixp425_imask[IPL_SOFTBIO] == 0);
+ KASSERT(ixp425_imask[IPL_SOFTNET] == 0);
+ KASSERT(ixp425_imask[IPL_SOFTSERIAL] == 0);
#endif
/*
@@ -233,10 +238,6 @@
* limited input buffer space/"real-time" requirements) a better
* chance at not dropping data.
*/
- ixp425_imask[IPL_SOFTBIO] |= ixp425_imask[IPL_SOFTCLOCK];
- ixp425_imask[IPL_SOFTNET] |= ixp425_imask[IPL_SOFTBIO];
- ixp425_imask[IPL_SOFTSERIAL] |= ixp425_imask[IPL_SOFTNET];
- ixp425_imask[IPL_VM] |= ixp425_imask[IPL_SOFTSERIAL];
ixp425_imask[IPL_SCHED] |= ixp425_imask[IPL_VM];
ixp425_imask[IPL_HIGH] |= ixp425_imask[IPL_SCHED];
Index: arm/xscale/pxa2x0_intr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/pxa2x0_intr.c,v
retrieving revision 1.16
diff -u -r1.16 pxa2x0_intr.c
--- arm/xscale/pxa2x0_intr.c 5 Sep 2009 17:40:35 -0000 1.16
+++ arm/xscale/pxa2x0_intr.c 2 Jun 2010 14:49:48 -0000
@@ -238,17 +238,13 @@
pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */
for( ; i < NIPL-1; ++i)
- pxa2x0_imask[i] &= ~mask; /* Disable itnerrupt at upper level */
+ pxa2x0_imask[i] &= ~mask; /* Disable interrupt at upper level */
/*
* Enforce a hierarchy that gives "slow" device (or devices with
* limited input buffer space/"real-time" requirements) a better
* chance at not dropping data.
*/
- pxa2x0_imask[IPL_SOFTBIO] &= pxa2x0_imask[IPL_SOFTCLOCK];
- pxa2x0_imask[IPL_SOFTNET] &= pxa2x0_imask[IPL_SOFTBIO];
- pxa2x0_imask[IPL_SOFTSERIAL] &= pxa2x0_imask[IPL_SOFTNET];
- pxa2x0_imask[IPL_VM] &= pxa2x0_imask[IPL_SOFTSERIAL];
pxa2x0_imask[IPL_SCHED] &= pxa2x0_imask[IPL_VM];
pxa2x0_imask[IPL_HIGH] &= pxa2x0_imask[IPL_SCHED];
Index: evbarm/include/intr.h
===================================================================
RCS file: /cvsroot/src/sys/arch/evbarm/include/intr.h,v
retrieving revision 1.20
diff -u -r1.20 intr.h
--- evbarm/include/intr.h 27 Apr 2008 18:58:46 -0000 1.20
+++ evbarm/include/intr.h 2 Jun 2010 14:49:49 -0000
@@ -41,7 +41,6 @@
#ifdef _KERNEL
/* Interrupt priority "levels". */
-#ifdef __HAVE_FAST_SOFTINTS
#define IPL_NONE 0 /* nothing */
#define IPL_SOFTCLOCK 1 /* clock */
#define IPL_SOFTBIO 2 /* block I/O */
@@ -52,18 +51,6 @@
#define IPL_HIGH 7 /* everything */
#define NIPL 8
-#else
-#define IPL_NONE 0 /* nothing */
-#define IPL_SOFTCLOCK IPL_NONE /* clock */
-#define IPL_SOFTBIO IPL_NONE /* block I/O */
-#define IPL_SOFTNET IPL_NONE /* software network interrupt */
-#define IPL_SOFTSERIAL IPL_NONE /* software serial interrupt */
-#define IPL_VM 1 /* memory allocation */
-#define IPL_SCHED 2 /* clock interrupt */
-#define IPL_HIGH 3 /* everything */
-
-#define NIPL 4
-#endif
/* Interrupt sharing types. */
#define IST_NONE 0 /* none */
Index: hpcarm/include/intr.h
===================================================================
RCS file: /cvsroot/src/sys/arch/hpcarm/include/intr.h,v
retrieving revision 1.13
diff -u -r1.13 intr.h
--- hpcarm/include/intr.h 17 Apr 2010 13:36:21 -0000 1.13
+++ hpcarm/include/intr.h 2 Jun 2010 14:49:49 -0000
@@ -38,7 +38,6 @@
#ifdef _KERNEL
-#ifdef __HAVE_FAST_SOFTINTS
#define IPL_NONE 0
#define IPL_SOFTCLOCK 1
#define IPL_SOFTBIO 2
@@ -49,18 +48,6 @@
#define IPL_HIGH 7
#define NIPL 8
-#else
-#define IPL_NONE 0
-#define IPL_SOFTCLOCK IPL_NONE
-#define IPL_SOFTBIO IPL_NONE
-#define IPL_SOFTNET IPL_NONE
-#define IPL_SOFTSERIAL IPL_NONE
-#define IPL_VM 1
-#define IPL_SCHED 2
-#define IPL_HIGH 3
-
-#define NIPL 4
-#endif
#define IST_UNUSABLE -1 /* interrupt cannot be used */
#define IST_NONE 0 /* none (dummy) */
Index: shark/include/intr.h
===================================================================
RCS file: /cvsroot/src/sys/arch/shark/include/intr.h,v
retrieving revision 1.9
diff -u -r1.9 intr.h
--- shark/include/intr.h 27 Apr 2008 18:58:47 -0000 1.9
+++ shark/include/intr.h 2 Jun 2010 14:49:52 -0000
@@ -37,7 +37,6 @@
#define _SHARK_INTR_H_
#define IPL_NONE 0
-#ifdef __HAVE_FAST_SOFTINTS
#define IPL_SOFTCLOCK 1
#define IPL_SOFTBIO 2
#define IPL_SOFTNET 3
@@ -47,17 +46,6 @@
#define IPL_HIGH 7
#define NIPL 8
-#else
-#define IPL_SOFTCLOCK IPL_NONE
-#define IPL_SOFTBIO IPL_NONE
-#define IPL_SOFTNET IPL_NONE
-#define IPL_SOFTSERIAL IPL_NONE
-#define IPL_VM 1
-#define IPL_SCHED 2
-#define IPL_HIGH 3
-
-#define NIPL 4
-#endif
#define IST_UNUSABLE -1 /* interrupt cannot be used */
#define IST_NONE 0 /* none (dummy) */
---
Izumi Tsutsui
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