bin/38679: cpuctl should display L3 cache info on AMD Family 10h

[paul%whooppee.com@localhost]

>Number:         38679
>Category:       bin
>Synopsis:       cpuctl should display L3 cache info on AMD Family 10h
>Confidential:   no
>Severity:       non-critical
>Priority:       medium
>Responsible:    bin-bug-people
>State:          open
>Class:          change-request
>Submitter-Id:   net
>Arrival-Date:   Sat May 17 15:40:00 +0000 2008
>Originator:     Paul Goyette
>Release:        NetBSD 4.99.62
>Organization:
----------------------------------------------------------------------
|   Paul Goyette   | PGP DSS Key fingerprint: |  E-mail addresses:   |
| Customer Service | FA29 0E3B 35AF E8AE 6651 |  paul%whooppee.com@localhost   |
| Network Engineer | 0786 F758 55DE 53BA 7731 | pgoyette%juniper.net@localhost |
----------------------------------------------------------------------
>Environment:
        
        
System: NetBSD quicky.whooppee.com 4.99.62 NetBSD 4.99.62 (QUICKY (ASUS M2N32 
WS) 2008-05-14 13:20:42) #1: Wed May 14 06:25:08 PDT 2008 
paul%speedy.whooppee.com@localhost:/build/obj/amd64/sys/arch/amd64/compile/QUICKY
 amd64
Architecture: x86_64
Machine: amd64
>Description:
        cpuctl does not currently display L3 cache info
>How-To-Repeat:
>Fix:
The following patch will display L3 cache info on AMD Family 10h
Index: i386.c
===================================================================
RCS file: /cvsroot/src/usr.sbin/cpuctl/arch/i386.c,v
retrieving revision 1.3
diff -u -p -r1.3 i386.c
--- i386.c      15 May 2008 23:31:56 -0000      1.3
+++ i386.c      17 May 2008 15:33:12 -0000
@@ -101,8 +101,9 @@ struct x86_cache_info {
 #define        CAI_ICACHE      4               /* Instruction cache */
 #define        CAI_DCACHE      5               /* Data cache */
 #define        CAI_L2CACHE     6               /* Level 2 cache */
+#define        CAI_L3CACHE     7               /* Level 3 cache */
 
-#define        CAI_COUNT       7
+#define        CAI_COUNT       8
 
 /*
  * AMD Cache Info:
@@ -182,6 +183,12 @@ struct x86_cache_info {
 #define        AMD_L2_ECX_C_LPT(x)              (((x) >> 8)  & 0xf)
 #define        AMD_L2_ECX_C_LS(x)               ( (x)        & 0xff)
 
+/* L3 Cache */
+#define        AMD_L3_EDX_C_SIZE(x)            ((((x) >> 18) & 0x3fff) * 512 * 
1024)
+#define        AMD_L3_EDX_C_ASSOC(x)            (((x) >> 12) & 0xf)
+#define        AMD_L3_EDX_C_LPT(x)              (((x) >> 8)  & 0xf)
+#define        AMD_L3_EDX_C_LS(x)               ( (x)        & 0xff)
+
 /*
  * VIA Cache Info:
  *
@@ -1796,6 +1819,23 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
                cai->cai_associativity = cp->cai_associativity;
        else
                cai->cai_associativity = 0;     /* XXX Unknown/reserved */
+
+       /*
+        * Determine L3 cache info on AMD Family 10h processors
+        */
+       if (family == 0x10) {
+               cai = &ci->ci_cinfo[CAI_L3CACHE];
+               cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]);
+               cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]);
+               cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]);
+
+               cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
+                   cai->cai_associativity);
+               if (cp != NULL)
+                       cai->cai_associativity = cp->cai_associativity;
+               else
+                       cai->cai_associativity = 0;     /* XXX Unkn/Rsvd */
+       }
 }
 
 static void
@@ -1905,4 +1945,9 @@ x86_print_cacheinfo(struct cpu_info *ci)
                if (sep != NULL)
                        aprint_verbose("\n");
        }
+       if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) {
+               sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL);
+               if (sep != NULL)
+                       aprint_verbose("\n");
+       }
 }

>Unformatted: