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Re: ACPI call for testing

> On Wed, Aug 25, 2010 at 03:57:32PM +0200, Wolfgang Solfrank wrote:
> > Ok, turns out that interrupts aren't really blocked, but that the CPU
> > has a bug (AMD erratum #400) that makes it not wake up from C1E or C3
> > sleep state from a lapic timer interrupt. 
> We have been pondering with this some time now. The conclusion from the
> last
> round was that there seems to be no way to "overcome" the AMD C1E easily
> without having what is needed for functional C-states generally.
> With the "normal" C3-state -- which is really just renamed as C1E by AMD
> --
> the operating system has some control over when to enter this deep sleep-
> state and what to do with the APIC/TSC timer issues. This is impossible
> with AMD C1E.

The correct workaround is to
a) implement the OSVW feature
b) use OSVW to detect Errata 400. When present then switch away
   from the LAPIC timer before entering HLT.


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