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Re: enhanced speed step on AMD64

On Mon, May 24, 2010 at 12:06:23AM +0200, Joerg Sonnenberger wrote:
> On Sun, May 23, 2010 at 09:59:09PM +0000, Christos Zoulas wrote:
> > That's not the problem. The EST code really needs to go because
> > it is ~impossible to figure out the proper thing to do from the MSR's.
> It can't go. There are a lot of slightly older systems where the ACPI
> implementation is basically useless. Just because Intel decided to f**k
> up and move it back to hidden magic (didn't they learn from Speedstep?)
> doesn't mean the old interface doesn't work for those CPUs it applies
> to.

Can anybody describe where "we" are at for supporting speedstep on CPUs
like the i7, then? Will it require an entire new framework to support? Can
somebody describe where the "problem" exists between this hardware and
the current NetBSD support for Speedstep on it? I'm interested both for
the practical matter of getting this CPU supported, and it's something
I just don't know anything about, so a "teachable moment" :)


Brad Harder
Method Logic Digital Consulting

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