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Re: enhanced speed step on AMD64

On Sun, 23 May 2010, wrote:

> Yup, and none of that works -- I've got a Pentium M with speedstep
> successfully running, so I'm aware of the interface, etc. Was wondering
> if something changed in the meantime that I missed... I'll leave this
> thread out there in the hope that someone can shed some light, or set
> me on the right path...

reading the code (at arch/x86/x86/est.c) seems to indicate that "boot -x"
should cause _some_ kind of message to be emitted if the est_init()
function is called. You could also build a kernel with "options EST_DEBUG"
which will print more..

Then, the code that calls est_init() (in arch/x86/x86/identcpu.c) shows

        if (cpu_feature[1] & CPUID2_EST) {
                if (rdmsr(MSR_MISC_ENABLE) & (1 << 16))

and on my machine, "cpuctl identify 0" shows

  cpu0: features2 0xc1a9<SSE3,MONITOR,VMX,EST,TM2,xTPR,PDCM>

I don't know what MSR_MISC_ENABLE means, perhaps just that the CPU is


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