tech-net archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
Re: NetBSD 5.1 RC1 wm0 with Xen 4.0.0
> In message <100808015822.M0104231%mirage.ceres.dti.ne.jp@localhost>
> on Sun, 8 Aug 2010 01:58:22 +0900,
> Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost> wrote:
> >> > >> wm0 at pci0 dev 4 function 0: Intel i82540EM 1000BASE-T Ethernet, rev
> >> > >> 3
> >> > >> wm0: interrupting at ioapic0 pin 32
> >> > >> wm0: 32-bit 33Mhz PCI bus
> >> > >> wm0: No EEPROM
> >> > >> wm0: unable to read Ethernet address
> >> > >
> >> > > Just FYI, qemu-0.12.3 seems to have the similar problem:
> >> >
> >> > Since I am based on qemu-0.11.0 it is maybe the reason why.... :)
> >> >
> >> > Maybe NetBSD can handle better a different nic?
> >>
> >> Or fix qemu?
> >
> > FYI, qemu-0.13.x will include a fix for this problem.
> > (i.e. NetBSD's wm(4) will work on it)
> Is there any work around by NetBSD side?
Here it is:
Index: if_wm.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/if_wm.c,v
retrieving revision 1.214
diff -u -p -r1.214 if_wm.c
--- if_wm.c 26 Jul 2010 22:33:24 -0000 1.214
+++ if_wm.c 10 Sep 2010 12:46:23 -0000
@@ -4518,6 +4518,14 @@ wm_read_eeprom_uwire(struct wm_softc *sc
reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI);
CSR_WRITE(sc, WMREG_EECD, reg);
+ /* XXX: workaround for a bug in qemu-0.12.x and prior */
+ reg |= EECD_SK;
+ CSR_WRITE(sc, WMREG_EECD, reg);
+ reg &= ~EECD_SK;
+ CSR_WRITE(sc, WMREG_EECD, reg);
+ delay(2);
+ /* XXX: end of workaround */
+
/* Set CHIP SELECT. */
reg |= EECD_CS;
CSR_WRITE(sc, WMREG_EECD, reg);
---
I wonder how we can detect if running host is QEMU in the driver...
(i82540EM + MAC, or enable the workaround once after EEPROM fails without it?)
---
Izumi Tsutsui
Home |
Main Index |
Thread Index |
Old Index