Re: workaround intel apollo lake errata

[Maxime Villard <max%m00nbsd.net@localhost>]

Le 01/07/2018 à 10:39, coypu%sdf.org@localhost a écrit :
> Hi,
>
> Currently Apollo Lake CPUs fail to boot with SMP enabled.[1]
> This is because we use MONITOR/MWAIT with interrupts disabled for
> waiting for secondary CPUs to hatch.
> Errata means the wakeup doesn't happen.[2]
>
> I've written the attached patch, and tested it by matching my existing
> CPU which doesn't have this problem. I see monitor is disabled early
> enough.
>
> Due to the first patch failing I know this means that ACPI C FFH won't
> be used[3][4]. I suspect this use is safer because it is with interrupts
> enabled.
>
> (I'm not sure how to name the MISC_ENABLES register value thing)
>
> Is this diff acceptable?

Pay attention to 325384-sdm-vol-3abcd.pdf, page 1314/2008:

	"If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit 0] = 0),
	 the OS must not attempt to alter this bit. BIOS must leave it in the
	 default state. Writing this bit when the SSE3 feature flag is set to
	 0 may generate a #GP exception."

Are you sure the affected family-model-stepping CPUs have the SSE3 feature
flag? Because if they don't you can't clear the bit.

Otherwise it doesn't look incorrect to me. However you may want to reapply the
wrmsr after an ACPI wakeup, because chances are it got reset. But I guess it
doesn't matter a lot since there are countless MSRs we don't reapply, so it's
not like it's not already broken.