Re: Access to DMA memory while DMA in progress?

[<Paul.Koning%dell.com@localhost>]

> On Oct 27, 2017, at 10:36 AM, Mouse <mouse%Rodents-Montreal.ORG@localhost> wrote:
> 
>>> I would like to read the DMA buffer while DMA is still going on.
>>> [...]  I'm fine if the CPU's view lags the hardware's view slightly,
>>> but I do care about the CPU's view of the DMA write order matching
>>> the hardware's: that is, if the CPU sees the value written by a
>>> given DMA cycle, then the CPU must also see the values written by
>>> all previous DMA cycles.
>> I'm not sure if that requirement is necessarily supported by hardware.  For $
> 
> Hm!  On such hardware, then, you can't count on any particular portion
> of a DMA transfer being visible until the whole transfer is finished?

Yes.  I'm assuming here that the driver would do a data cache invalidate
(for the address range, if possible) at DMA end.  Given that, during the
transfer you would see pieces that weren't in the cache before, and would
not see pieces for which there are cache hits.

> For my purposes, unelss amd64 is such a platform, I'm willing to write
> off portability to such machines.  Is there any way to detect them from
> within the driver?  I could just ignore the issue, but I'd prefer to
> give an error at attach time.

I don't know much about x86 style platforms.  An example of the sort of
platform I mentioned would be the MIPS R5000.  I still have some scars
from building a fast router on top of its incoherent DMA...

	paul