On Mon 24 Nov 2014 at 16:56:44 +0000, Taylor R Campbell wrote: > Just to clarify a tiny bit: TAILQ_FOREACH uses data-dependent loads, > no matter what CPU architecture it runs on. A data-dependent load is > anything like what CPU 2 is doing here: > > CPU 1 CPU 2 > > A = 0 > A = 5 > membar_producer() > *pp = &A > p = *pp > v = *p <--- Data-dependent load: > load address depends on > data from previous load. > > On most CPU architectures, v is guaranteed to be 5; on alpha, if you I must admit that it is not clear to me how on all these architectures the CPU is to know in general that *p depends on p = *pp. I can imagine that this is possible in trivial cases like this, when simply compiled as (let's use PDP-11 syntax) mov _pp,r0 mov (r0),r1 ; r1 is p mov (r1),r2 ; r2 is v but in more complex cases where r1 is moved to another register before indirection, or has some constant or variable added to it or even more complex calculations, this seems far from clear to me. It seems that the Alpha case would actually be more realistic in general. Structs can be very large, so p->far_away_field can address memory quite far away from where p points. Simply discarding a cache line when p is loaded into a register seems neither necessary (->inefficient) nor sufficient. > want v to be 5, you must insert a membar_consumer between `p = *pp' > and `v = *p'. -Olaf. -- ___ Olaf 'Rhialto' Seibert -- The Doctor: No, 'eureka' is Greek for \X/ rhialto/at/xs4all.nl -- 'this bath is too hot.'
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