Re: 4byte aligned com(4) and PCI_MAPREG_TYPE_MEM

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

mrg@ wrote:

> > Such byte lane offset adjust ment is required only if
> > - byte registers are wired to LSByte in 32bit bus
> > - byte lane wiring are swapped by hardware (like osiop(4))
> > but most (all?) PCI bus_space(9) implementations swap
> > byteorder of PCI access by software (i.e. in MD bus_space(9)).
> 
> FYI:  not all -- sparc64 either maps PCI space as little
> endian or uses little endian accesses, both of which give
> you the byte swapped data directly.

Even in that case, the hardware checks access width and
all byte accesses can be done at the same address
as the little endian machines by complicated hardware
(i.e. #if BYTE_ORDER in the patch won't work), right?

---
Izumi Tsutsui