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Re: re(4) MAC address



Frank Wille wrote:

(sorry for delay)

> > IIRC RTL8139 doc says the chip reads the values from EEPROM automatically.
> > We should follow what 8169 doc specifies, but I don't have 8169 docs.
> 
> I checked the 8169 doc. In the EEPROM section there is the following
> description for EEPROM address 0xe - 0x13:
> 
> "Ethernet ID: After auto-load command or hardware reset, the RTL8169
> loads Ethernet ID to IDR0-IDR5 of the RTL8169's I/O registers."
> 
> As that happens automatically after reset, I would suggest that re(4)
> should trust IDR0-IDR5 for the correct address, and not try to access
> the EEPROM itself - which might be missing.

The attached patch make re(4) always use IDR register values
for its MAC address.

We no longer have to link rtl81x9.c for eeprom read functions
and I'm not sure if we should make the old behavoir optional
or remove completely.

But for now I think it's almost harmless so please commit
if it works on re(4) on your NAS boxes.

---
Index: conf/files
===================================================================
RCS file: /cvsroot/src/sys/conf/files,v
retrieving revision 1.1061
diff -u -p -r1.1061 files
--- conf/files  14 Nov 2012 02:03:25 -0000      1.1061
+++ conf/files  28 Dec 2012 14:24:20 -0000
@@ -943,7 +943,7 @@ file        dev/ic/rtl80x9.c                rtl80x9         
        needs-f
 # Realtek 8129/8139 Ethernet controllers
 #
 device rtk: ether, ifnet, arp, mii
-file   dev/ic/rtl81x9.c                rtk | re
+file   dev/ic/rtl81x9.c                rtk
 
 # Realtek 8169 Ethernet controllers
 #
Index: dev/ic/rtl8169.c
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/rtl8169.c,v
retrieving revision 1.136
diff -u -p -r1.136 rtl8169.c
--- dev/ic/rtl8169.c    22 Jul 2012 14:32:57 -0000      1.136
+++ dev/ic/rtl8169.c    28 Dec 2012 14:24:21 -0000
@@ -554,9 +554,8 @@ void
 re_attach(struct rtk_softc *sc)
 {
        uint8_t eaddr[ETHER_ADDR_LEN];
-       uint16_t val;
        struct ifnet *ifp;
-       int error = 0, i, addr_len;
+       int error = 0, i;
 
        if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
                uint32_t hwrev;
@@ -643,6 +642,12 @@ re_attach(struct rtk_softc *sc)
        /* Reset the adapter. */
        re_reset(sc);
 
+       /*
+        * RTL81x9 chips automatically read EEPROM to init MAC address, and
+        * some NAS override its MAC address per own configuration, so
+        * so no need to explicitely read EEPROM and set ID registers.
+        */
+#if 0
        if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) {
                /*
                 * Get station address from ID registers.
@@ -650,6 +655,9 @@ re_attach(struct rtk_softc *sc)
                for (i = 0; i < ETHER_ADDR_LEN; i++)
                        eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
        } else {
+               uint16_t val;
+               int addr_len;
+
                /*
                 * Get station address from the EEPROM.
                 */
@@ -667,6 +675,13 @@ re_attach(struct rtk_softc *sc)
                        eaddr[(i * 2) + 1] = val >> 8;
                }
        }
+#else
+       /*
+        * Get station address from ID registers.
+        */
+       for (i = 0; i < ETHER_ADDR_LEN; i++)
+               eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
+#endif
 
        /* Take PHY out of power down mode. */
        if ((sc->sc_quirk & RTKQ_PHYWAKE_PM) != 0)
@@ -1725,11 +1740,13 @@ static int
 re_init(struct ifnet *ifp)
 {
        struct rtk_softc *sc = ifp->if_softc;
-       const uint8_t *enaddr;
        uint32_t rxcfg = 0;
-       uint32_t reg;
        uint16_t cfg;
        int error;
+#if 0
+       const uint8_t *enaddr;
+       uint32_t reg;
+#endif
 
        if ((error = re_enable(sc)) != 0)
                goto out;
@@ -1774,6 +1791,7 @@ re_init(struct ifnet *ifp)
 
        DELAY(10000);
 
+#if 0
        /*
         * Init our MAC address.  Even though the chipset
         * documentation doesn't mention it, we need to enter "Config
@@ -1787,6 +1805,7 @@ re_init(struct ifnet *ifp)
        reg = enaddr[4] | (enaddr[5] << 8);
        CSR_WRITE_4(sc, RTK_IDR4, reg);
        CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF);
+#endif
 
        /*
         * For C+ mode, initialize the RX descriptors and mbufs.

---
Izumi Tsutsui


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