Re: TLB tiredown by ASID bump

[Matt Thomas <matt%3am-software.com@localhost>]

On Jan 5, 2011, at 6:41 PM, Toru Nishimura wrote:

> There are growing number of CPU architecture which have
> ASID to extend TLB VA->PA translation and improve runtime
> TLB efficiency.  ASID switching is the least cost MMU
> operation to make multiple processes run simultaneously.
> ASID eliminates the necessity to discard whole TLB context
> on each context switch.

The ASID generational stuff has a downside in that valid 
entries will be thrown away.  For mips (and booke) I use
a different algorithm which eliminates the overhead of
discarding all the TLB entries when you run out of ASIDs.

ASIDs are allocated from low to high.  If the allocation
bitmap shows that ASID has been allocated, the next ASID 
is tried.  Once the ASID hits its limit, the TLB is scanned 
for all active ASIDS and the allocation bitmap is updated
accordingly.  Then the list of active ASIDs is scanned.  If
the pmap has an ASID that still has matching entries in the
TLB (its bit is set in the allocation bitmap), that ASID 
stays allocated.  If a pmap has an ASID that is no longer 
in the TLB (corresponding bit is clear), that the pmap's ASID 
is discarded and the pmap will get a new on its next activation.
If the TLB contains entries with ASIDs that don't match any current
pmap, those ASIDs are left allocated and will not be allocated
for this pass (but will be eventually reaped as those TLB entries
are overwritten with new ASIDs).

If there's aren't enough free ASIDs (but that rarely, if ever, 
happens), then the ASID pool is emptied and everyone gets a 
fresh ASID on their next pmap activation.

> I would propose here to add a new hook in exception return
> path for every NetBSD ports.  The hook point is at right
> after ast() call.  The hook is to call TLB ASID bump op
> (to write EntryHi with a single mtc0 instruction for MIPS
> architecture , for example).   It should be noted that the
> hook is also useful to do "isync operation" for the process
> which needs to invalidate instruction cache to continue.

It's not really needed and doesn't do the right thing anyways.