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re: 5.99.30 sparc panic during startup
> It looks multiple interrupt handlers against the same interrupt level
> are properly queued and handled in sparc/intr.c:ih_insert(), so
> no need to prepare own queue in zs.c.
this patch must be tested on a system with both serial usage and
zskbd/zsms working, and if possible, on a system with more than
2 zs controllers.
my understanding from the way that sparc and zs interrupts work
is that the hardware _does not tell you_ which chip interrupted,
that's why you have to check them all. you get an interrupt at
level 12 and that's it.. i suspect it works for you because
the right "zsc_softc" is being passed down by luck.
(i'd love to be wrong.)
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