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Re: IPLs - One too many?
On Fri, Jul 25, 2008 at 10:29:03AM +0100, Chris Gilbert wrote:
> Matt Thomas wrote:
> > I've been talking to Chris Gilbert for a while about eliminating nested
> > interrupts in one or more of the ARM ports.
> > Ignoring IPL_SOFT* IPLs for the moment, ARM currently has
> > IPL_NONE < IPL_VM < IPL_SCHED < IPL_HIGH
> > Since IPL_SCHED == IPL_CLOCK, once IPL_SCHED is reached you block
> > clock interrupts. Since clock interrupts are the highest priority
> > interrupts, you have basically blocked all interrupts. So there
> > is little difference between IPL_HIGH and IPL_SCHED.
> > So why have both? Can I just make IPL_HIGH == IPL_SCHED?
> > This means I have three IPL value, IPL_NONE, IPL_VM, IPL_HIGH.
> > And now I can directly map those to the ARM CPSR bits IF32_bits
> > (IRQ, FIQ) as 00, 10, 11 so I can make IPL_NONE=0, IPL_VM=2, and
> > IPL_HIGH=3 and have no reason to store a s/w copy of the IPL since
> > the CPU status word will contain an encoding of it.
> > Much/All of the IRQ/FIQ enable/disable in the kernel can then just
> > become spl calls.
> For those less familiar with ARM hardware, ARM cpus have two interrupt
> lines, called IRQ and FIQ. FIQs have priority over IRQs.
The other detail being (and I always forget this and get confused) is
that the polarity of the IRQ/FIQ bits are such that a 0 is an enable.
Though it doesn't make a difference to the broad meaning of Matt's
proposal, it hopefully explains the values for IRQ/FIQ bits and how
they map to IPLs.
Time is an illusion; lunchtime, doubly so. |/\/\| Rafal Boni
-- Ford Prefect |\/\/|
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