Re: Non power-of-two cache sizes and page colouring

[Simon Burge <simonb%NetBSD.org@localhost>]

Izumi Tsutsui wrote:

> simonb%NetBSD.org@localhost wrote:
> 
> > It's reported as:
> > 
> >    cpu0: L2 cache 6 MB 64B/line 16-way
> 
> I'm not sure where the value comes from
> (don't we use the CPUID instruction?), but
> "AP-485 Intel(R) Processor Identification and the CPUID Instruction"
> http://www.intel.com/design/processor/applnots/241618.htm
> has no such combination but does an entry of
> "2nd-level cache: 6MB, 24-way set associative, 64-byte line size."

I can't correlate anything in that document about working out cache info
with what x86/x86/cacheinfo.c does.  At this stage I'm entirely prepared
to believe NetBSD doesn't know what it's doing with cache info :-)

CPUID(0x80000006) doesn't list 24-way as an option in Table 3-17, and
yet Table 3-7 does (the line you quoted above).  It looks like we should
use CPUID(2) and then look that up in a table built from Table 3-7.  I
haven't looked at any AMD info, but I wonder if we should be using a new
intel_cpu_cacheinfo() on Intel chips and use CPUID(2) instead?

I think we're also trying to use CPUID(0x80000005) to work out the L1
cache info, but that is marked as "Reserved" in that document.  I'm not
sure if that's an AMDism or not...

Cheers,
Simon.