Re: Non power-of-two cache sizes and page colouring

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

simonb%NetBSD.org@localhost wrote:

> It's reported as:
> 
>    cpu0: L2 cache 6 MB 64B/line 16-way

I'm not sure where the value comes from
(don't we use the CPUID instruction?), but
"AP-485 Intel(R) Processor Identification and the CPUID Instruction"
http://www.intel.com/design/processor/applnots/241618.htm
has no such combination but does an entry of
"2nd-level cache: 6MB, 24-way set associative, 64-byte line size."
---
Izumi Tsutsui