tech-embed archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

Re: PC104 ADC programming problem

Christos Eleftheriadis wrote:
Greetings to the list,

Has anyone came across of the below behaviour ?

The platform I use for a project is a TS7200, based around the cirrus
logic EP3902.
The SBC has a PC104 expansion connector. On the connector sits a 12
bit ADC board of the same company...

Small programs that initiate a single ADC conversion work like a dream..
My problem starts when I want to pool data at higher speeds...
I have not been able to go above 30 samples/sec.

sys/arch/arm/ep93xx/epclk.c only supports 64Hz for process scheduling,
your program can only get half that using sleep.  Jitter may already
be significant, depending on the other hardware in the system.

The SBC runs a kernel compiled from CVS some weeks ago.
Do I need to tweak the kernel files in some point ?
Or this is the higher speed that a userland program can go ?

Should I try to write a driver to achieve the speed I want ? 50Ksps
would be OK for me..
The manufacture company says that 100Ksps are feasible...and the ADC
chip can do 125Ksps

You'd have to configure one of the other processor timers to
drive the conversion, and pass the data up in blocks (see the
serial drivers or audio drivers for examples).  Then there's
still a high probability that you'd have to rewrite the kernel's
interrupt handling in order to reduce jitter in the sample rate
to where the data is usable.

below is the code that I am testing.. it is quite small
The time that elapses between the printfs` is 1 sec

Any suggestions, recommendations would be greatly appreciated

A USB sound card?

Try using eCOS:


Home | Main Index | Thread Index | Old Index